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Intel Nova Lake (16th gen) on next gen platform/socket (LGA-1954)

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Back to 15% improvement over Intel 3 (last year they gave a more conservative number) at ISO-Power. AP should provide another 5%.

At 1.1V, 25% more frequency.

Process seems very good, and if it's healthy it's up to the design team to not drop the ball.

This is very promising!
 
imo ht is bad and ecores are bad, there should only be pcores, all cores should be identical.
if I was intel that's what I'd do anyway.

Big little is a means to an end. Sadly the windows market will start to suck once Intel finds a core design that competes well enough with Zen and support for big little is dropped.
 
ONdASm8.png


Back to 15% improvement over Intel 3 (last year they gave a more conservative number) at ISO-Power. AP should provide another 5%.

At 1.1V, 25% more frequency.

Process seems very good, and if it's healthy it's up to the design team to not drop the ball.

Blackwell is crying out for a fix like this.
 
imo ht is bad and ecores are bad, there should only be pcores, all cores should be identical.
if I was intel that's what I'd do anyway.
Hyperthreading isn't bad if you're talking about total throughput.
It depends what you want. If you want a small number of threads running as fast as possible, then SMT off is probably the right way. But in server world, it's more about total throughput.

I don't think HT will ever go away, if anything we may see a jump to 3 or 4 threads per core.
The main problem is CPU cores have vast amounts of resources, so that in very small tightly optimised loops the performance is great. But the other 90% of the time the core is barely 50% used. That's not a good use of CPU space. This is why SMT was invented.

There's talk of rentable unit's architecture, but fundamentally it's a very difficult conundrum to solve.
If you add more resources, how to you make sure they're aren't sitting there unused most of the time ?
If you take away resources and have more cores instead, you hobble single core performance, and total performance if the software doesn't scale perfectly to all cores.
 
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Intel Nova Lake performance leak claims 10% single and 60% multi-threaded uplift​


 
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Intel Nova Lake performance leak claims 10% single and 60% multi-threaded uplift​



If this is to be believed then whats the point in Arrow Lake refresh... 10% in single thread for Nova Lake should be minimum for Arrow Lake refesh.

Even the 60% in multithread is not that great as I would think the multi threading would be higher if that 60% increase is the 52 core 385K vs the 24 core 285K.
 
If this is to be believed then whats the point in Arrow Lake refresh... 10% in single thread for Nova Lake should be minimum for Arrow Lake refesh.

Even the 60% in multithread is not that great as I would think the multi threading would be higher if that 60% increase is the 52 core 385K vs the 24 core 285K.

Arrow Lake refresh (just a clock speed bump and to force reviewers to re-test with all new firmware/driver/game optimisations) is just so that Intel have something to release in 2025.

Nova Lake is 2026 and may be delayed to 2027 knowing Intel.
 
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If this is to be believed then whats the point in Arrow Lake refresh... 10% in single thread for Nova Lake should be minimum for Arrow Lake refesh.

Even the 60% in multithread is not that great as I would think the multi threading would be higher if that 60% increase is the 52 core 385K vs the 24 core 285K.

Most of the new cores on the 385k are E cores and new LP cores, these have far less performance than P cores and it's likely the 385k has the same P cores count as 285k. This is why double the core count does not give double the performance
 
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Most of the new cores on the 385k are E cores and new LP cores, these have far less performance than P cores and it's likely the 385k has the same P cores count as 285k. This is why double the core count does not give double the performance

They have also removed SMT, which will result in a loss, but that's offset against the IPC increase.

The E cores in ARL are based on Skymont, and they are more or less on par with RPL in terms of performance, but they are more optimised for lower power. However, Nova Lake will bring a new Cove and Mont microarchitecture along with bLLC

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If they have corrected the Cache & IO issues, it should be quite performant. You can work around some of those losses with an increase to the ring, D2D and NGU on ARL. Reading about Pantherlake (new Cove and Mont), they seem to have addressed those issues, but we shall see once those are released and testing has been done.
 

Interesting. If Intel's confident of there being overwhelming demand for NovaLake, it should truly be something special and the shakeup we need in the CPU world.

It's very boring with Zen5X3D being so much ahead of Intel.
 
Some of this was already known/posted about - but still some news bits

Intel "Nova Lake-S" Core Ultra 3, Ultra 5, Ultra 7, and Ultra 9 Core Configurations Surface


28 core i5 is pretty wild!

TechPowerUp said:
Intel will be significantly increasing CPU core counts with its next-generation "Nova Lake" client processor microarchitecture. For the desktop variant, the "Nova Lake-S," this marks a maximum CPU core configuration of 16P+32E+4LPE for an impressive 52 cores per socket. That's 16 "Coyote Cove" P-cores, 32 "Arctic Wolf" E-cores spread across eight E-core clusters; and 4 additional low-power island E-cores based on the same "Arctic Wolf" core design. While the P-cores and E-core clusters share an L3 cache, the LPE cores are not part of the CPU complex, and are located in a low-power island that's part of the SoC region of the chip, an arrangement similar to "Meteor Lake." The top Core Ultra 9 is expected to come with a massive L3 cache of 144 MB, which should benefit gaming workloads.

Intel will give only its top Core Ultra 9 SKUs the maxed out configuration of 16P+32E+4LPE. This chip is expected to come with a processor base power value of 150 W for its unlocked K or KF SKUs. We are now learning what the core configurations of the other brand extensions, 7, 5, and 3, could look like. For the Core Ultra 7 SKUs, Intel is expected to opt for a 14P+24E+4LPE configuration for a total of 42 cores. To do this, the company will disable two P-cores, and two E-core clusters, while also reducing the L3 cache. The top K- and KF-SKUs of Core Ultra 7 are expected to come with the same 150 W processor base power values as the Core Ultra 9 K/KF SKUs.

Things get very interesting with the Core Ultra 5 "Nova Lake-S" series. Intel is dialing up the core-counts it's held onto for three generations, and giving the top Core Ultra 5 K/KF series chips an 8P+16E+4LPE core configuration, for a 28-core per socket product. There will also be a non-K/KF SKU with 8P+12E+4LPE configuration, and a lower-end Core Ultra 5 SKU with 6P+8E+4LPE. We're not sure if this is based on physically the same chip as the Core Ultra 9, or if Intel is developing a physically smaller Compute tile. The SoC tile with 4 LPE cores are expected to remain the same. The Core Ultra 5 series will hence come with three core configurations depending on the processor model—8P+16E+4LPE for the top K/KF SKUs, 8P+12E+4LPE for the non-K/KF top SKUs, and 6P+8E+4LPE for the lower-end SKU.

We now move into the value segment, and Intel is planning to address this with two Core Ultra 3 processor types. The upper SKU comes with 4P+8E+4LPE configuration (16 cores) with 65 W processor base power. At the very entry level, is a SKU with 4P+4E+4LPE (12 cores), with 65 W base power.

As for platform I/O, Intel tends to keep its connectivity consistent across processor brand extensions, differentiated only by the motherboard chipset models. With its top chipset model, the "Nova Lake-S" platform is expected to offer a total of 32 PCI-Express 5.0 lanes, and a total of 16 PCI-Express 4.0 lanes. It is likely that Intel updates the chipset bus with newer DMI 5.0 for bandwidth resembling PCI-Express 5.0 x8 for the top chipset model, and PCI-Express 5.0 x4 for the mid-tier chipset model.

The iGPU of "Nova Lake-S" is expected to be based on the Xe3 "Celestial" graphics architecture for generational performance gains, although this will be a smaller iGPU than the one expected to feature in the mobile H-segment and U-segment variants of "Nova Lake." All processor models are expected to come with an NPU that meets Microsoft Copilot+ local acceleration requirements.

Intel is expected to debut "Nova Lake-S" in 2026.
 
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