Chipset
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Upstream LDT Bus Width - [16 bit] 8 bit
Downstream LDT Bus Width - [16 bit] 8 bit
LDT Bus Frequency - [600hz] 800mhz, 600mhz, 400mhz, 200mhz
VLink Mode Selection - [By Auto] Mode 0, Mode 1, Mode 2, Mode 3, Mode 4
PEG Data Scrambling - [Auto] Disable, Enable
PE0-PE3 Data Scrambling - [Enable] Disable
Init Display First - [PCI Slot] PCIEx
Chipset Vcore Adjustment - [+1.5V] +1.5V to +1.6V
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DRAM Config
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Timing Mode - [Manual] Auto
Memclock Index Value - [133mhz] 200mhz, 166mhz, 133mhz, 100mhz
CAS# Latency (Tcl) - [2.5] 2, 3
Min RAS# active time (Tras) - [7T] 5T to 15T
RAS# to CAS# delay (Trcd) - [3T] 2T to 7T
Row Precharge time (Trp) [3T] 2T to 7T
1T/2T Memory Timing - [1T] 1T
MTRR mapping Mode - [Continuous] Discrete
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Jumperfree Config
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Overclocking Profile - [Manual] Auto, Standard, AI OC, AI ***
CPU Multiplier - [10x] Auto, 4x to 11.5x
Hammer vid control - [1.4125] 1.45V and lower
Memory voltage adjustment - [2.8V] 2.6V to 3.0V
CPU VCore offset - [+100mv] +200mv
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Frequency Config
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Spread Spectrum - [Disable] Auto, Enable
PCIEx Clock sync to CPU [Disabled]
PCIEx clock 100mhz
PCI clock sync to CPU [Disabled]
PCI clock 33mhz
CPU Clock - [260mhz] from 200mhz to 400mhz