8 PACK MEMORY RANGE GROWING: SAY HELLO TO 8 PACK RIPPED EDITION & 32GB KITS!!!

Yeah that would make sense for what ive seen from the xxxx_sg values ive seen posted in various screenshots for intel rigs. There is clearly some sort of parallel there, but AMD appear to handle it differently. Not being able to adjust RTLs on the AMD side means you have to play the board so it auto sets your desired values - its the only way you know the RTLs are correct. I'm sure what you posted above will be really useful for any of the Intel users however, its definitely not out of place in the context of the discussion but doesn't seem to directly apply to AMD.

The one advantage I suppose AMD does have is that it controls AGESA which is the base building block for all AMD bioses. It means settings are always comparable between boards until you get down to manufacturer specific tweaks (mainly Crosshair boards). It does mean no access to the real fine tuning options (such as RTLs) that Intel have had for years on their Z and X chipset boards. Easy mode memory overclocking once you learn to look for the indicators your board isn't happy training, but you can't push RTLs hard to gain latency back.
 
There some manufactures like GB on intel don't let you hardset RTL's for example and are generally avoided. If you're keen on mem oc, I can extend you an invite to a discord group. It's mainly 50/50 amd/intel and more focused technical discussions on OC'ing. No 'wars' etc allowed.
 
That sounds fun...though I'm trying to resist picking up a C14 3800 G.Skill set at the moment so it may not be a financially sound decision... Would love to join though :). I tend to lurk mostly and its only when something really piques my interest that I get tempted to post these days.

I've only been playing with AMD for a year, before that I had every Intel generation from Northwood up to z77, then went x58, x79 and finally x99/Haswell-E... Fancied a change as much as anything else but the memory side has been disappointingly simple. Its like early DDR3 days, with an ITX board half the tertiarys don't apply and due to AMD's architecture a lot of the secondaries and tertiarys are fixed at minimums (whether by ratio of other timings or "chipset" limits) anyway. The C14 3800 purchase would be as much to see if TRCD 15 @ 1:1 max mhz and unthrottled is a chipset limit or down to really hard binning.
 
@MrPils doesn't let me message you directly. Message me and i can share the invite.

I'm now very comfortable with timings so my next challenges is learning park/nom/vtt voltage tuning to get higher frequencies.
 
Updated to the latest bios and had a go at doing some memory tuning. Previously achieved 16-16-16-34 with RAM @ 3800MHz but without messing with secondary or other timings.

This is what I managed:
Xr9Oy6N.png

I was surprised with achieving this, as previously any messing about with secondary timings and it would not boot. I initially disabled XMP which gave me a blue screen; re-enabling it booted just fine and ran all the benches okay. I did 1 pass of memtest86, I will let the PC do a few runs tonight before I go to sleep.

Another thing to note I used Thaiphoon Burner to extract my latencies to then feed into the DRAM calculator. Worked a treat.

Edit: Managed to properly embed the screengrab.
 
Last edited:
MrPils said:
That sounds fun...though I'm trying to resist picking up a C14 3800 G.Skill set at the moment so it may not be a financially sound decision... Would love to join though :). I tend to lurk mostly and its only when something really piques my interest that I get tempted to post these days.

I've only been playing with AMD for a year, before that I had every Intel generation from Northwood up to z77, then went x58, x79 and finally x99/Haswell-E... Fancied a change as much as anything else but the memory side has been disappointingly simple. Its like early DDR3 days, with an ITX board half the tertiarys don't apply and due to AMD's architecture a lot of the secondaries and tertiarys are fixed at minimums (whether by ratio of other timings or "chipset" limits) anyway. The C14 3800 purchase would be as much to see if TRCD 15 @ 1:1 max mhz and unthrottled is a chipset limit or down to really hard binning.
Click to expand...
Can you recommend anyway i can improve performance/timings over what i have? Bearing in mind my CPU sample does not appear to like 1900FCLK. It boots, there are no audio issues when using it, but restarts randomly so i have settled on 1800FCLK and trying to tune memory as tight as possible. DRAM at 1.45v.
gOGdSO7.png

Is this as tuned as it can go or am i leaving performance on the table somewhere?

trcdrd at 15 to help gain stability.
 
LtMatt said:
Can you recommend anyway i can improve performance/timings over what i have? Bearing in mind my CPU sample does not appear to like 1900FCLK. It boots, there are no audio issues when using it, but restarts randomly so i have settled on 1800FCLK and trying to tune memory as tight as possible. DRAM at 1.45v.
gOGdSO7.png

Is this as tuned as it can go or am i leaving performance on the table somewhere?

trcdrd at 15 to help gain stability.
Click to expand...

Apologies - lost internet after the storm then had a couple of crazy busy days afterwards...

Anyway, thats a pretty good tune you have their already, there's not a huge amount more to gain I don't think. I take it from trdwr and twrrd being set to 18 and 7 that these are the 3600mhz 16-16-16 16gb sticks? It seems OCUK have tried to do something clever with the spd for Intel to auto set tRDWR and tWRRD without realising AMD doesn't work the same way. If you have XMP enabled, disable it and see if you can get board Auto values to load for those timings, they should be way lower. I'm not sure exactly how impactful they are, but they seem to be around double what I run with single sided. My (OLD!!) 16gb sticks ran these timings around 11 / 2 or 10 / 3 for whatever that is worth.

Aside from that minor faux pas caused by the SPD programming you can tighten up a couple of bits and pieces...

tRCDRW 8 should be possible on all B-Die
I haven't found B-Die yet that won't run tRP at least 1 below tCL, so you should be able to drop that to 13 or maybe even 12. That will allow you to reduce tRC and tRFC too.
tWR 10 will allow tRTP 5, however tWR 10 can work as a limit to your memory tune so make sure you test at 12 to see if you can further reduce more significantly impactful timings.

Tertiary timings:

Split your tertiary's into tRDRD based timings and tWRWR based timings. I have guessed at the meanings below, testing seems to back up my guesswork, but don't take these as gospel.

SCL's set Same Channel Latency (latency between channels - affects all setups using more than 1 stick)
SC if for Same Channel Different Dimm data transfers (latency between dimms if using two dimms per channel - affects 4 dimms setups only)
SD is for Same Dimm data transfers (latency between banks within the same dimm - affects double sided dimms only)
DD if for Different Dimm data transfers (latency between different dimms in different channels - affects all setups using more than 1 stick)

If you are using 2 x 8gb most of those timings wont be used so can be set to 1, with 4 x 8, 2 x 16 or 4 x 16 though you will need to explore your limits.

Method:

1) Reduce SCL's to minimum first. You'll usually find they both like being set to the same thing, SCL at 2 should be the target but may not be possible.
2) Once SCL's are minimised you can start reducing your RDRD and WRWR subtimings - you don't need to test these much, they should either be obviously unstable or fine. I reduce the lot by 1 and quick test each time. When I find instability I go back up to the last stable setting and start reducing the timings individually. Don't bother doing individual tuning of these timings from the start, it'll take ages.


I would try and aim for 3733mhz 1:1 if you can. 3800mhz IF booting means you are very close to stable - it probably just wants stupid voltage (so don't risk your 3950x trying). My cpu wont even post at 3800 IF yet 3733mhz is fully stable at reasonable volts. For reference, my voltage scaling with IF:

3200mhz 0.7vCCD, 0.7vDDG, 0.7vDDP (vSOC 1v stable @ 3200mhz)
3466mhz 0.775vCCD, 0.825vDDG, 0.8vDDP
3600mhz 0.825vCCD, 0.9vDDG, 0.9vDDP
3666mhz 0.825vCCD, 0.95vDDG, 0.925vDDP
3733mhz 0.85vCCD, 1.0vDDG, 0.95vDDP

vSOC I run at default (1.1v) with LLC set to mode 2 (2nd highest). Haven't needed to bump it on this 3900XT, though my earlier X cpus do need this voltage bumping to stop crackling audio at high IF. My 3800x for example requires 1.2vSOC for 3800mhz IF. 2 x 16gb may be harder on this voltage so I would probably do all the clocking at 1.2v then dial it down at the end.


If you want the final 0.5% once you have done all your other tweaking you can carefully test breaking the tRAS minimum rule. Go slowly as you can corrupt your hdd if you reduce tRAS/tRFC too low too quickly. Test for performance loss as well, things can get weird when breaking timing rules. I haven't been able to stabilise tRAS 21 (chipset minimum) yet, but tRAS 22 is stable on all my B-die at up to 3800mhz. This lets you pull tRC down to 36 and tRFC to 252 (or 216/220 if you can get down that low, but that's close to if not within corruption territory for 16gb dimms).

You have nearly all of your possible memory performance already, you're not leaving much on the table if you were to stop where you are now :).

GL dude :)
 
MrPils said:
Apologies - lost internet after the storm then had a couple of crazy busy days afterwards...

Anyway, thats a pretty good tune you have their already, there's not a huge amount more to gain I don't think. I take it from trdwr and twrrd being set to 18 and 7 that these are the 3600mhz 16-16-16 16gb sticks? It seems OCUK have tried to do something clever with the spd for Intel to auto set tRDWR and tWRRD without realising AMD doesn't work the same way. If you have XMP enabled, disable it and see if you can get board Auto values to load for those timings, they should be way lower. I'm not sure exactly how impactful they are, but they seem to be around double what I run with single sided. My (OLD!!) 16gb sticks ran these timings around 11 / 2 or 10 / 3 for whatever that is worth.

Aside from that minor faux pas caused by the SPD programming you can tighten up a couple of bits and pieces...

tRCDRW 8 should be possible on all B-Die
I haven't found B-Die yet that won't run tRP at least 1 below tCL, so you should be able to drop that to 13 or maybe even 12. That will allow you to reduce tRC and tRFC too.
tWR 10 will allow tRTP 5, however tWR 10 can work as a limit to your memory tune so make sure you test at 12 to see if you can further reduce more significantly impactful timings.

Tertiary timings:

Split your tertiary's into tRDRD based timings and tWRWR based timings. I have guessed at the meanings below, testing seems to back up my guesswork, but don't take these as gospel.

SCL's set Same Channel Latency (latency between channels - affects all setups using more than 1 stick)
SC if for Same Channel Different Dimm data transfers (latency between dimms if using two dimms per channel - affects 4 dimms setups only)
SD is for Same Dimm data transfers (latency between banks within the same dimm - affects double sided dimms only)
DD if for Different Dimm data transfers (latency between different dimms in different channels - affects all setups using more than 1 stick)

If you are using 2 x 8gb most of those timings wont be used so can be set to 1, with 4 x 8, 2 x 16 or 4 x 16 though you will need to explore your limits.

Method:

1) Reduce SCL's to minimum first. You'll usually find they both like being set to the same thing, SCL at 2 should be the target but may not be possible.
2) Once SCL's are minimised you can start reducing your RDRD and WRWR subtimings - you don't need to test these much, they should either be obviously unstable or fine. I reduce the lot by 1 and quick test each time. When I find instability I go back up to the last stable setting and start reducing the timings individually. Don't bother doing individual tuning of these timings from the start, it'll take ages.


I would try and aim for 3733mhz 1:1 if you can. 3800mhz IF booting means you are very close to stable - it probably just wants stupid voltage (so don't risk your 3950x trying). My cpu wont even post at 3800 IF yet 3733mhz is fully stable at reasonable volts. For reference, my voltage scaling with IF:

3200mhz 0.7vCCD, 0.7vDDG, 0.7vDDP (vSOC 1v stable @ 3200mhz)
3466mhz 0.775vCCD, 0.825vDDG, 0.8vDDP
3600mhz 0.825vCCD, 0.9vDDG, 0.9vDDP
3666mhz 0.825vCCD, 0.95vDDG, 0.925vDDP
3733mhz 0.85vCCD, 1.0vDDG, 0.95vDDP

vSOC I run at default (1.1v) with LLC set to mode 2 (2nd highest). Haven't needed to bump it on this 3900XT, though my earlier X cpus do need this voltage bumping to stop crackling audio at high IF. My 3800x for example requires 1.2vSOC for 3800mhz IF. 2 x 16gb may be harder on this voltage so I would probably do all the clocking at 1.2v then dial it down at the end.


If you want the final 0.5% once you have done all your other tweaking you can carefully test breaking the tRAS minimum rule. Go slowly as you can corrupt your hdd if you reduce tRAS/tRFC too low too quickly. Test for performance loss as well, things can get weird when breaking timing rules. I haven't been able to stabilise tRAS 21 (chipset minimum) yet, but tRAS 22 is stable on all my B-die at up to 3800mhz. This lets you pull tRC down to 36 and tRFC to 252 (or 216/220 if you can get down that low, but that's close to if not within corruption territory for 16gb dimms).

You have nearly all of your possible memory performance already, you're not leaving much on the table if you were to stop where you are now :).

GL dude :)
Click to expand...
Thanks, that's really helpful. I'll see what i can glean from your post to see if i can improve anything.

I am using 8Pack 3600Mhz CL14 sticks.

It's odd, i don't recall seeing any timings in the BIOS running at 18 and 7 for trdwr and twrrd.

I might grab some screenshots to post in my next reply. I may be back with more questions. :p
 
MrPils said:
SNIP
Click to expand...
As above, i have some follow up questions you can hopefully answer. :)

1. Which timing in the screenshots below is tRCDRW which can be reduced to 8? I assumed its called something different in the BIOS. I believe one of the screenshots ive attached below will show it. Figured this one out myself
2. Which timing in the screenshot is TRP which can be reduced to 1 below CL? Figured this one out myself.
3. This question related to screenshot 4 and voltages. You say vCCD at 0.85v for your IF overclock, in my screenshot is that both values that i have set at 0.850v? If so, what is VDDG voltage? Do you see that in screenshot 4?
4. Ryzen DRAM Calculator suggests values of 8 and 3 for TRDWR and TWRRD, however i have now selected 11/2 as per your suggested settings for my 4x8GB sticks. Do you recommend i use the DRAM Calc settings or yours?

Pictures
AGcQWQP.jpg

86rr1Mr.jpg

9DCosN1.jpg

Ek4IjgL.jpg
 
Last edited:
LtMatt said:
As above, i have some follow up questions you can hopefully answer. :)

1. Which timing in the screenshots below is tRCDRW which can be reduced to 8? I assumed its called something different in the BIOS. I believe one of the screenshots ive attached below will show it. Figured this one out myself
2. Which timing in the screenshot is TRP which can be reduced to 1 below CL? Figured this one out myself.
3. This question related to screenshot 4 and voltages. You say vCCD at 0.85v for your IF overclock, in my screenshot is that both values that i have set at 0.850v? If so, what is VDDG voltage? Do you see that in screenshot 4?
4. Ryzen DRAM Calculator suggests values of 8 and 3 for TRDWR and TWRRD, however i have now selected 11/2 as per your suggested settings for my 4x8GB sticks. Do you recommend i use the DRAM Calc settings or yours?
Click to expand...

Regards voltages - I fudged that up so I wasn't clear enough, my bad... vDDG CCD is for the infinity fabric link between the chiplets. This one rarely needs much extra voltage at all, 0.85v is usually fine right up to 3800mhz. vDDG IOD is the voltage for the fabric link between the IO die and the chiplets...this is the one that needs voltage increases (and the voltage I referred to as vDDG). This voltage is derived from your vSOC voltage, so is limited to a maximum of 50mv below vSOC. Frequently chips will require this voltage to be 1150mv or so to stabilise 3800mhz IF. This is safe but the result is that your vSOC must be at least 1.2v (also safe...but hot). LLC on your vSOC voltage affects both vDDG voltages, it helps to have LLC on the SOC voltage one step down from maximum. In terms of real world maximum voltages SOC at 1.25v and vDDG at 1.2v is fine for benching and stability testing, but I wouldn't chose to run those voltages daily personally. I have nothing empirical against that, just feels high to me for a daily.

A good daily voltage setup would be 1.1vSOC, 1050mv vDDG IOD, 950mv vDDP, 850mv vDDG CCD. You may need to monitor your SOC voltage and adjust it up a little to maintain the 50mv gap, 4 sticks may pull it down a little under load (and impact vDDG as a result).

Question 4.... All I can really offer in answer to that is that if the cumulative total of TRDWR and TWRRD is lower then its faster. 8/3 should be faster if its stable simply due to maths (8+3=11 < 11+2=13), I found best performance in synthetics and stability tests to be running TWRRD at 1 and then TRDWR as low as it will go based on that. I always leave these values on auto until last, but then my auto values are never that far off (and are usually actually what I want to manually set anyway). If you go one too low cumulatively you'll get errors in membench default, two too low and itll no post. Tweaking the balance between the timings can apparently help stability but I've never had to play with it really.

You'll get a nice latency boost from tweaking the other tertiary timings, be prepared for very sudden no posts though, once you go too tight on those then it just doesn't train at all. Save profiles and you'll be fine, as soon as you hit a no post go from adjusting them all down a notch at a time to doing each timing separately. I suspect you'll get a couple down to 1 as you're running single sided :). Both SCL's to 2 is the best boost.
 
Last edited:
You must log in or register to reply here.
Back
Top Bottom