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AMD announce EPYC

ChrisD. said:
I’d expect a lot of it is done in memory. Storage can’t keep up with those numbers!
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Indeed, I've used dedicated devices that communicate directly into the PCI-E bus, and then to a RAM disk and that is committed to disk at a slower speed.

They must have some serious kit to divvy up 40Tbs though.
 
Journey said:
Indeed, I've used dedicated devices that communicate directly into the PCI-E bus, and then to a RAM disk and that is committed to disk at a slower speed.

They must have some serious kit to divvy up 40Tbs though.
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It’ll be multiple CentOS or Red Hat boxes working as a ‘supercomputer’ is my guess. RAM shared across all boxes and they all do a piece each.
 
I would expect it's around 50 EPYC servers to get 40Tbit/s. This is raw infiniband throughout rather than storage capacity. Likely that are streaming the data and processing or before storing a much smaller version of it. I've been working on some storage using EPYC servers that's capable of 80GB/s read and 60GB/s out of all flash nvme drives and only 6 EPYC servers to create this storage.
 
Seriously can't wait for Milan now, a software dev who I work with had a meeting with a MS bod yesterday and they were chatting about the scaling of the servers for cloud based applications, and he said and I'll indirect quote "You've seen nothing, these CPU's a simply next level for us (MS) in all aspects, density, performance, TCO."

I dread to think what Genoa is going to do with 5nm, DDR5, PCI-E 5.0 and the potential to have up to 128c/512t on a single socket system, Datcentre in a box compared with 5 years ago, well almost. :p
 
Journey said:
I dread to think what Genoa is going to do with 5nm, DDR5, PCI-E 5.0 and the potential to have up to 128c/512t on a single socket system.
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I wonder how feasible that will be?
The scaling to 5nm is less than double the transistor budget over 7nm so the individual chiplets will surely have to be significantly larger in size.
What with added features and the less than 2x scaling will there be enough room for 8 of them?
Depends partly on the I/O hub and how close they can package them.
I was wondering if AMD do go to 16C chiplets whether they will keep them for Threadripper and Epyc for a year or longer.

ARM have just announced two new server platforms and one will use lighter cores so will probably scale to 128C per socket whilst the other will probably 'only' scale to 96C per socket.
Unless AMD take a dual prong approach like ARM root they will have to decide which market to focus on.
 
smilingcrow said:
I wonder how feasible that will be?
The scaling to 5nm is less than double the transistor budget over 7nm so the individual chiplets will surely have to be significantly larger in size.
What with added features and the less than 2x scaling will there be enough room for 8 of them?
Depends partly on the I/O hub and how close they can package them.
I was wondering if AMD do go to 16C chiplets whether they will keep them for Threadripper and Epyc for a year or longer.

ARM have just announced two new server platforms and one will use lighter cores so will probably scale to 128C per socket whilst the other will probably 'only' scale to 96C per socket.
Unless AMD take a dual prong approach like ARM root they will have to decide which market to focus on.
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One core in a N7 CCX is approximately 3.756 mm²
https://www.anandtech.com/show/14525/amd-zen-2-microarchitecture-analysis-ryzen-3000-and-epyc-rome/5

Chiplet is 74 mm², it has 2 CCXs each 31.3 mm², around 50% is cores and 50% L3 cache.
 
smilingcrow said:
I wonder how feasible that will be?
The scaling to 5nm is less than double the transistor budget over 7nm so the individual chiplets will surely have to be significantly larger in size.
Click to expand...

Seems like some of the space may be saved by downsizing the I/O die, and slightly increasing the package size of each Zen4 chiplet. They'll also be changing socket so they have room to move to a bigger package overall if they wish.
 
Journey said:
Seriously can't wait for Milan now, a software dev who I work with had a meeting with a MS bod yesterday and they were chatting about the scaling of the servers for cloud based applications, and he said and I'll indirect quote "You've seen nothing, these CPU's a simply next level for us (MS) in all aspects, density, performance, TCO."

I dread to think what Genoa is going to do with 5nm, DDR5, PCI-E 5.0 and the potential to have up to 128c/512t on a single socket system, Datcentre in a box compared with 5 years ago, well almost. :p
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Got me a server to drop a couple of these bad boys into. Quite excited to see Milan and what she does :) I really don't need the performance over Rome but you can be sure ill take it!
 
Vince said:
Got me a server to drop a couple of these bad boys into. Quite excited to see Milan and what she does :) I really don't need the performance over Rome but you can be sure ill take it!
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I'm not in a position to do anything with Milan until 2021 sadly, and even then it may be Q2, which is a really shame. I'll just have to love vicariously through you and others who have hands on with them early in the product life cycle.

If they can achieve 15% more performance on average over X workloads, then that is the equivalent of going from 64 cores to ~74 cores for the same space and maybe slightly less power, exciting times.
 
Just an FYI to those who have not see it (and kind of related to security post above)

If you drop a new Epyc CPU in certain servers (e.g Dell) you cannot subsequently use it in other brands of server due to one time security fuses being blown.

It appears that HPE are not doing this yet (Dell might not be doing it in all lines either), but looks like something else to research if making a second hand purchase - good article here: https://www.servethehome.com/amd-psb-vendor-locks-epyc-cpus-for-enhanced-security-at-a-cost/
 
It's amazing to see how far EPYC has come in a few short years, and the article below shows the expandability on offer compared with competing systems, not that they can even hold a candle to this, 160 PCIE 4.0 lanes on one system and the engineering and ideas that have been put in place to allow this to be made are epic/EPYC? :)

Article is well worth a read if you are interested in how things are coming along.

https://www.servethehome.com/dell-and-amd-showcase-future-of-servers-160-pcie-lane-design/
 
Journey said:
It's amazing to see how far EPYC has come in a few short years, and the article below shows the expandability on offer compared with competing systems, not that they can even hold a candle to this, 160 PCIE 4.0 lanes on one system and the engineering and ideas that have been put in place to allow this to be made are epic/EPYC? :)

Article is well worth a read if you are interested in how things are coming along.

https://www.servethehome.com/dell-and-amd-showcase-future-of-servers-160-pcie-lane-design/
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Right now AMD have almost every CPU segment under their control in terms of performance and features and price also usually.
Maybe the one area where it isn't so clear cut is desktop CPUs under £400 and definitely desktop APUs which are still MIA.
I can't think of any other family of architectures that have been so massively dominant in so many sectors at the same time.
An amazing achievement.
 
Any news on 5000 series EPYC? Id imagine they are going to be insane quite frankly
 
ZP9 said:
Thanks!

And yeah my bad thats what I meant haha! Meant to say Zen3 architecture
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I don't even need one as I have a bunch of Rome servers but the temptation is immense. So long as I can jab one into my gen10's ill take a couple for sure :D
 
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