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*** AMD "Zen" thread (inc AM4/APU discussion) ***

Guys, ZEn is focused against LGA1151. not against LGA2011-v3. Zen has 95W TDP, the same as Skylake.
AMD cant fight now with ultrahighend, how many customers, gamers, enthusiast bought LGA2011? Im sure, 90% of enthusiast bought LGA1150 core i7 or core i5 in K version.
AMD need first most of them for income.
PCIe 3.0 is enough for 2016, there will be not PCIe 4.0 card. And 2017 is Zen+ architecture. Now are PCIe lines in CPU, not in chipset aka northbridge as old AM3 boards
 
humbug said:
Lol. Do some studies before throwing your weight around next time.

In prical terms it saves space, functionality it enable the two CU's and thier indervidual FPU's to join up to make one big CU and thread, in that you can have one big CU + FPU doing the bard work with 6 remaining doing multiple little jobs, or 2 + 4 ecte....
Click to expand...

In practical terms, it wasn't as good as individual fat cores, as borne out by various benchmarks and real world findings. I am not saying there is no merit to resource sharing, there clearly is, BD/PD just wasn't as good as everyone hoped.

Math does not lie, martini has shown where the deficits are several times, with sound reasoning. Many benchmarks and compilers are skewed towards Intel uarch but that does not stop AMD's module designs being inferior to Intel's in what enthusiasts want from their chip. This is coming from an AMD user (although not exclusively)since the heady days of the Duron
 
Both Zen and Skylake release too late for me to bother with them, especially as I need a (to build) PC next month. But in the future, I may just try out AMD processors if their claims on performance are correct and they provide better value for money than Intel.

AthlonXP1800 said:
16 lanes! Really very disappointed! Zen FX cant compete with Ivy Bridge-E so it put Zen FX at same level as Ivy Bridge with 16 lanes PCI Express 3.0 while Ivy Bridge-E and Haswell-E has up to 40 lanes. Skylake will have 20 lanes.

Cant wait for Skylake.
Click to expand...

This has me disappointed too. Skylake 20 lanes still doesn't make sense as we still get 8x/8x dual gpu, though it doesn't do much for performance apparently. All it adds is the possibility of 8x/8x/4x tri-Crossfire and maybe 8x/4x/4x/4x quad-Crossfire, but that's it. In that respect Zen FX could still compete against Skylake as it still has the same lanes for dual GPU. But more lanes on Skylake means better SLI compatible boards, Zen FX will be like current boards, with some (cheaper) not supporting SLI. I guess Skylake will let us use our 16x GPU and a PCIe device that uses 4 lanes.
 
d_brennen said:
In practical terms, it wasn't as good as individual fat cores, as borne out by various benchmarks and real world findings. I am not saying there is no merit to resource sharing, there clearly is, BD/PD just wasn't as good as everyone hoped.

Math does not lie, martini has shown where the deficits are several times, with sound reasoning. Many benchmarks and compilers are skewed towards Intel uarch but that does not stop AMD's module designs being inferior to Intel's in what enthusiasts want from their chip. This is coming from an AMD user (although not exclusively)since the heady days of the Duron
Click to expand...
Martini didnt know anything about it, he lost his cool when I explained the reasons for the single threaded results in cenebench and tried to say I don't know what I was talking about and did it in a way that's basically trolling, thats the reason for the 2 page argument.

I had already explained exactly what you are talking about long before the cenebench debarkle. :)


humbug said:
With 8 integer units AMD are very good with integer performance, any type of direct number crunching they are good strong CPU's.
They are actually a server CPU and much better suited to that.

Vishera is let down for things like gaming not so much because a lack of raw FP performance but because of they way its designed.

I said Vishera has 8 cores and 4 threads, thats not strictly true.

There is a reason for this "modular design" its innovative but in practical terms flawed.

Each module has 2 integer units and one or two FP threads depending on which configuration is called for.

For example.

Module Config:
#1, 2 Integer + 1 256Bit FP thread
#2, 2 Integer + 2 128Bit FP threads
#3, 1 Big Integer + 1 256Bit FP thread

The idea being that if you don't need so many threads you can have 4 fast ones, or if you need more threads you can have 8 slower ones, or you can have a combination of those.

But you have to code for that and its not that easy, whats more most compilers are setup for Intel.

A lot of times what you actually end up with is the two Integer units combined through one 128Bit FP, causing bottlenecks.

The fact is if AMD want to compete with Intel they have to design their CPU's to work in the same way as Intel.

There is just no desire for something different.

And it seems AMD have accepted that now with these Zen APU's
Click to expand...
 
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mahius said:
This has me disappointed too. Skylake 20 lanes still doesn't make sense as we still get 8x/8x dual gpu, though it doesn't do much for performance apparently. All it adds is the possibility of 8x/8x/4x tri-Crossfire and maybe 8x/4x/4x/4x quad-Crossfire, but that's it. In that respect Zen FX could still compete against Skylake as it still has the same lanes for dual GPU. But more lanes on Skylake means better SLI compatible boards, Zen FX will be like current boards, with some (cheaper) not supporting SLI. I guess Skylake will let us use our 16x GPU and a PCIe device that uses 4 lanes.
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20 lanes allows you 8x/8x while also using 4 lanes for e.g. a NVMe SSD - not likely a common setup, but still I'd rate 20 as a big improvement over 16 personally.
 
I can't see it being limited to 16 lanes. That would make no sense, given AMD have two, three and four card technology. It would cut them out of their own market.

Not only that but SLI must run at X8 or it doesn't work, so you'd literally be right on the limit.

If the CPU is only 16 lanes then I would imagine that AM4 has the extra lanes needed as part of the chipset.
 
ALXAndy said:
I can't see it being limited to 16 lanes. That would make no sense, given AMD have two, three and four card technology. It would cut them out of their own market.

Not only that but SLI must run at X8 or it doesn't work, so you'd literally be right on the limit.

If the CPU is only 16 lanes then I would imagine that AM4 has the extra lanes needed as part of the chipset.
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Definitely.

There'll be 2 or three chipsets, like with every modern platform. The entry one will just use CPU IO, the others will add function.

No point in loading too much onto the CPU when it won't always be used.
 
While it's true that you can buy a £1000 CPU to get enough lanes to run a quad GPU setup, it's still annoying having to worry about them and calculate, compromise, research etc.
 
ALXAndy said:
In their defence AMD make long lasting chipsets. I mean they're literally around for years, so they may be designing it so the chipset has the extra lanes.
Click to expand...

Err, you could argue the same for all chipsets ever made. AMD's current top end chipset for FX CPU's is the 990 series, released in 2011. It's very dated stuff - no native PCI-E v3, no native USB3, no M.2, no Sata Extress, nothing.

They still functionally work though, as do the older Intel chipsets, such as X58, released in 2008, sporting much the same specs as 990. The main difference being that Intel have since released x79, z87, z97, x99, and very soon z170.
 
humbug said:
In prical terms it saves space, functionality it enable the two CU's and thier indervidual FPU's to join up to make one big CU and thread, in that you can have one big CU + FPU doing the bard work with 6 remaining doing multiple little jobs, or 2 + 4 ecte....
Click to expand...

In reality, Sandy Bridge not only had a smaller die but also included an integrated GPU and performed much better in the majority of CPU based scenarios, compared to Sandy Bridge AMD's modular architecture it is a bloated mess and probably not any real improvement on the Phenom X6 before it if you take away the smaller process.

Bulldozer 1.2bn 315mm2
Sandy Bridge 1.16bn 216mm2 (inc. GPU)

If that's AMD saving space I'd hate to see them going for all out performance.

humbug said:
With 8 integer units AMD are very good with integer performance, any type of direct number crunching they are good strong CPU's.
Click to expand...

Again its integer performance (in a best case scenario which required excess multithreading) was no better than the smaller Sandy Bridge and its floating point performance much worse.
 
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mmj_uk said:
In reality, Sandy Bridge not only had a smaller die but also included an integrated GPU and performed much better in the majority of CPU based scenarios, compared to Sandy Bridge AMD's modular architecture it is a bloated mess and probably not any real improvement on the Phenom X6 before it if you take away the smaller process.

Bulldozer 1.2bn 315mm2
Sandy Bridge 1.16bn 216mm2 (inc. GPU)
Thuban 904M 346mm2

If that's AMD saving space I'd hate to them going all out.
Click to expand...

Unless you are assessing manufacturing economics it would be better (but by no means ideal) to look at transistor count rather than die, and probably compare against SB-E.

edit: re the igp according to anandtech the SB igp took 114bn transitors
http://www.anandtech.com/show/4083/...el-core-i7-2600k-i5-2500k-core-i3-2100-tested
-just below die shot, not sure if accurate
 
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mmj_uk said:
In reality, Sandy Bridge not only had a smaller die but also included an integrated GPU and performed much better in the majority of CPU based scenarios, compared to Sandy Bridge AMD's modular architecture it is a bloated mess and probably not any real improvement on the Phenom X6 before it if you take away the smaller process.

Bulldozer 1.2bn 315mm2
Sandy Bridge 1.16bn 216mm2 (inc. GPU)

If that's AMD saving space I'd hate to see them going for all out performance.



Again its integer performance (in a best case scenario which required excess multithreading) was no better than the smaller Sandy Bridge and its floating point performance much worse.
Click to expand...

I don't know why you are making comparisons to Intel given that i'm not, i'm simply explaining the architectural characteristics of Bulldozer / Piledriver.

Personally i would have preferred it if AMD had just stuck to basics, 4 to 6 fat cores with one nice wide 256Bit thread each.

That way they wouldn't have had this half a thread bottlenecked to hell because the application isn't treating it as AMD would like.... problem!

I'm not justifying anything AMD did here, they made a mistake, a rather silly one, perhaps in hindsight.

In any case it looks like AMD may have learnt a very hard lesson.
 
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