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*** AMD "Zen" thread (inc AM4/APU discussion) ***

jigger said:
Not telling me anything I don't know.
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...riiiiiight, but what I pointed out clearly invalidated your previous statement.

And I'm not sure how this thread got so derailed, all I said is that the infinity fabric for the Ryzen die is dreadful, 250% latency increase for the purpose of modularity, making future APU designs easier.
If their financials improve and they make specialized Zeppelin dies and APU ones they could remove IF from the die and get performance benefits that way, not sure why the Knights of AMD all got rustled.

For their Epyc/TR MCMs the IF is needed and should be iterated on since that allows them to be hyper-competitive on core counts, but for monolithic dies it comes with a performance impact.
 
AndreiD said:
...riiiiiight, but what I pointed out clearly invalidated your previous statement.

And I'm not sure how this thread got so derailed, all I said is that the infinity fabric for the Ryzen die is dreadful, 250% latency increase for the purpose of modularity, making future APU designs easier.
If their financials improve and they make specialized Zeppelin dies and APU ones they could remove IF from the die and get performance benefits that way, not sure why the Knights of AMD all got rustled.

For their Epyc/TR MCMs the IF is needed and should be iterated on since that allows them to be hyper-competitive on core counts, but for monolithic dies it comes with a performance impact.
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And people disagreed with you're statment for multiple reasons. I think mainly because you atempted to over ham the downsides...
 
His statement isn't wrong though. He is very correct in that it would be faster. How much more is questionable though. You would possibly need to look to the deactivated Ryzen cores tests for answers on that, although would it still have latency issues with the full cache in use?

However, right now for AMD, it was the perfect choice that allowed them a scaleable product stack in most market segments. Smart move.
 
How does removing IF from the die affect MCM scalability which is done via using PCI-E lanes? @jigger do you even know what IF does or how it works?
I'm pretty sure if AMD had the financials available they'd start making specialized dies, on die IF is a compromise for now.

100ns extra latency is nothing to scoff at for a desktop part, they'll need to tackle it somehow.
 
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AndreiD said:
IF latency is one of the big issues with the chips though, we already have old articles analyzing the latency impact.
Going from 40ns within CCX to 140ns CCX to CCX has some pretty big performance downsides and they could easily reap some IPC gains by removing it. It's a shame too since core to core latency within the same CCX is really good too.
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Yes it's a downside but it's only a huge if your software isn't optimised for the design. People shrug it off but we've had nearly 10 years of Intel dominance and iterations of pretty much the same CPU design, so developers are used to just optimising for a single architecture. Now more things need to be considered and these things take time. Look how many games got big performance boosts in the few months after Ryzen was released.

Another thing they may have the ability to do is change the 1:2 IF:RAM ratio to allow the infinity fabric to run at a higher frequency, that'd help too. At the end of the day though it's a small price to pay in exchange for AMD being able to make highly competitive products at fantastic prices (compared to the competition).

AndreiD said:
And when something comes with a 250% latency impact, it is pretty dreadful for that scenario.
And for Threadripper you have latency higher than dual socket Xeon systems because of it, it comes with plenty downsides.
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Have you ever written or used software designed for multi-socket high-core systems? You have to consider CPU layout when it comes to performance, basically keeping stuff on the right chip and in that chip's allocated RAM, and then even further down into the various caches. The same would be true of EPYC, it's not unusual.

Scougar said:
His statement isn't wrong though. He is very correct in that it would be faster. How much more is questionable though.
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As with everything it depends on the application. For single threaded stuff, which people always make sure to remind us that Intel dominates at because of their higher clock speeds, it'd make no difference. I'm sure there were some reviews early on that compared the 4+0 to 2+2 layout and I seem to remember it made not much difference. It was probably just game reviews I saw though, so not sure about other applications.
 
Because relying on developers to optimize for architectural 'quirks' has always turned out well...
A few titles did get patches for the unusually bad performance Ryzen had in them, but what about the thousands of older titles, will developers ever bother to update those? Relying on developers to optimize is always a losing strategy, and it's going to happen with Intel's Skylake-X too (mesh & cache hierarchy), it's never going to be properly utilized by consumer applications.

I do agree that on-die IF was necessary for AMD to be competitive, but that doesn't mean that they'll have to keep using it for all of their product stack once their financials improve.

And I think you missed the point of the dual socket latency comparison, it's noteworthy that a fabric between two dies on the same substrate has a higher latency impact. Here's an article on it: https://www.servethehome.com/amd-epyc-infinity-fabric-latency-ddr4-2400-v-2666-a-snapshot/ latency is similar to a 4P Xeon configuration, which isn't really ideal and AMD will have to tackle the issue for Zen+ or Zen 2.
Like you've said, decoupling it from DRAM frequency would be a good start, in my opinion they should remove it from desktop parts.
 
AndreiD said:
Because relying on developers to optimize for architectural 'quirks' has always turned out well...
A few titles did get patches for the unusually bad performance Ryzen had in them, but what about the thousands of older titles, will developers ever bother to update those? Relying on developers to optimize is always a losing strategy, and it's going to happen with Intel's Skylake-X too (mesh & cache hierarchy), it's never going to be properly utilized by consumer applications.

I do agree that on-die IF was necessary for AMD to be competitive, but that doesn't mean that they'll have to keep using it for all of their product stack once their financials improve.

And I think you missed the point of the dual socket latency comparison, it's noteworthy that a fabric between two dies on the same substrate has a higher latency impact. Here's an article on it: https://www.servethehome.com/amd-epyc-infinity-fabric-latency-ddr4-2400-v-2666-a-snapshot/ latency is similar to a 4P Xeon configuration, which isn't really ideal and AMD will have to tackle the issue for Zen+ or Zen 2.
Like you've said, decoupling it from DRAM frequency would be a good start, in my opinion they should remove it from desktop parts.
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The performance is great in all situations. AMD can make significant gains on Ryzen with increased clock speed. They can make even more significant gains if Ryzen plus is faster and cheaper than Ryzen.
 
jigger said:
The performance is great in all situations. AMD can make significant gains on Ryzen with increased clock speed. They can make even more significant gains if Ryzen plus is faster and cheaper than Ryzen.
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I wouldn't say all situations, sometimes it's very good other times it's quite bad. There are programs and games that just don't work very well on ryzen. Who knows how they will change that.
 
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