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- 29 Oct 2019
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Thanks, these settings worked well for me. I lowered tRFC to 560 and the voltages to 1.4v vDIMM, 0.95v cLDO_VDDG, 0.9v cLDO_VDDP. Seems very stable, passed an overnight Karhu RAMTest and a few hours TM5 with extreme config. I ran it for a while without changing the VDDG and VDDP voltages but realized that they were set to 1.15v and 1.1v when I can across this post, hopefully it didn't cause any harm. I tried setting vDIMM to 1.35v but it failed Karhu after 1 minute and TM5 started spitting out errors almost immediately.@MegaPinches these are the slightly updated ones which I think should work with most E-die kits & CPUs, should get you ~66ns in AIDA64 on a 2x SR kit:
tCL 16, tRCD(RD) 20, tRCD(WR) 20, tRP 16, tRAS 38, tRC 58
tRRDS 4, tRRDL, 6, tFAW 16, tWTRS 4, tWTRL 12, tWR 16, tRDRD SCL 4, tWRWR SCL 4, tRFC 580
tCWL 16, tRTP 12, tRDWR 9, tWRRD 2, tWRWR SC 1, tWRWR SD 7, tWRWR DD 7, tRDRD SC 1, tRDRD SD 5, tRDRD DD 5, tCKE 1 (or leave tCKE auto)
{tPage Auto, tRFC2 Auto, tRFC4 Auto}
ProcODT 40 Ohm, CMD2T 1T, GearDownMode Enabled, PowerDownMode Disabled
RTT, CAD Bus settings all on Auto
Voltages: 1.45v vDIMM (VTT should be half vDIMM, but on auto it's set to half anyway), 1.1v vSOC, 1.05v cLDO_VDDG, 1v cLDO_VDDP
If stuttering, up vSoC to 1.125v and VDDG to 1.075v (that fixed it for me). Loosened some tertiaries just to be on the safe side and from what I noticed lowering a few timings too much can actually have a negative impact on latency.
Here is my benchmark