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Reality|Bites said:
nope, just listing the results listed in the picture.
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Are you the man that types these words:

Because of the way that test works.

It bypasses the CPU and only tests the memory bandwidth.

Results are listed as

Memory bandwidth

CPU L1 bandwidth

CPU L2 bandwidth

The test is run between the memory controller and the Memory. not memory to CPU

Data travels CPU - NB - Memory (intel) and vice versa

For AMD it's just CPU - Memory.

I've had enough of you now really, You are just on the wind up.
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guess 'reality' really does 'bite' for some people. ;)

well Reality|Bites where does the L1 and L2 cache reside for your system? on the hard drive?

lol
 
you really need to backup the stuff your saying now pal. your cant argue with the maths and the logic.

even a 10 year old knows the L1 and L2 cache are on the cpu and not the hard drive or memory controller.

i have posted in this thread using facts and even maths to prove certain points. you havent been able to prove anything yet and are now resorting to insults. not the way to do things pal.
 
no just a serious question.

no insult intended.

I never said the L1 and L2 cache was anywhere apart from the CPU, you have mis-read what I typed.

What you are stating is that the 10GB/sec result from memory test is due to the quad pumped bus, I'm saying it is not. As it is a test run from the memory to the memory controller.
 
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practally nothing does anything inside a pc without the use of the cpu. if it were possible then the pc would run without a cpu in it.

another thing that shows that the cpu does have an effect in the bandwidth test is if you keep the same speed fsb and ram but alter the cpu multiplier in effect altering the cpu speed. and you will see that the memory bandwidth test will respond to the cpu clock speed, more clock speed will show up with more ram bandwidth. that shows that the cpu is used in the test and its not done from northbridge to memory.

even intel say that the fsb is quad pumped, why your saying that its not without sufficient evidence is very odd indeed.
 
Cyber-Mav said:
practally nothing does anything inside a pc without the use of the cpu. if it were possible then the pc would run without a cpu in it.

another thing that shows that the cpu does have an effect in the bandwidth test is if you keep the same speed fsb and ram but alter the cpu multiplier in effect altering the cpu speed. and you will see that the memory bandwidth test will respond to the cpu clock speed, more clock speed will show up with more ram bandwidth. that shows that the cpu is used in the test and its not done from northbridge to memory.

even intel say that the fsb is quad pumped, why your saying that its not without sufficient evidence is very odd indeed.
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I think he is trying to say that the FSB to the Northbridge (and therefore the memory controller) is quad pumped, but after that, it is not. Although I am sure it is, but I've never really thought about it.

On first thought though, the Northbridge communicates with the memory again at the set internal clock so in the case of a 'Quad 1600MHz' it's clock will be 400MHz. It communicates at 128-bit (2* 64-bit links) with the RAM, and each one of those is a DDR communication, so that does equal the bit level performance (well theoretical maximum) of the 'Quad-FSB'.

Unless he means that the 'Quad-FSB' is in essence communicating with just the Northbridge, and it in-turn is communicating with many more things, other than the RAM alone. Which will obviously mean it will take a slight hit as regards memory performance when more than just RAM is being communicated with. And so a test to show the bandwidth between the memory and memory controller should technically always be a bigger value than one testing the complete throughput to the CPU aswell.

If it's neither of those, then I've no idea. But it is a quad pumped bus. It exchanges data 4 times per clock. Maybe he is disputing the fact it's a theoretical? I don't know, but it's still really classed as 1600MHz, even if it doesn't come super close to that It's unlikely to be very far off. I mean DDR800 DDR is still 800MHz really, even if it cannot maintain it's full theoretical throughput.

But Cyber-Mav your calculations assume SDR-RAM. DDR doubles the transfer throughput. You have the calculation correct except you are using the Memory chip clock not the I/O clock, which is the 800MHz on an 800MHz chip, and branded packs of PC2-6400 are the theoretical maximumbandwidth per stick, not per set of sticks.

Bandwidth calculation: (memory bus width/8 bits) x data rate (hence the Doubling)

Theoretical maximum for a set of PC2-6400 sticks in Dual channel mode will therefore be 12800MB/s, assuming a latency free (and therefore never attainable) environment. Although looking back through the thread Isee you hae had this pointed out ot you and you realised the mistake.

So this brings me onto 1 question. What are we discussing exactly?
 
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It all started with MAV saying that for a true 1:1 ratio with a 1333Mhz fsb CPU(333 x 4)
You need DDR3 1333(667Mhz) memory.

Where I said you only need PC5300 to run a true 1:1 ratio

A 1066Mhz(266Mhz) only needed PC4200. So what's changed?
 
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