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Possible Radeon 390X / 390 and 380X Spec / Benchmark (do not hotlink images!!!!!!)

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Besty said:
For Nvidia that all-in margin figure is 11.64%, it was around 15% in 2011.

You can't really use that figure in the context of this question because it has all sorts of deductions in there and it can also be negatively manipulated by in-efficiencies in the company as much as R&D. Gross margin is the best per product figure to use in order to determine how much money a company generates off a given product.

To get an understanding of per card profit vs. R&D cost you need to look at in a per quarterly fashion. Nvidia spends around $1.3BN USD per year on R&D investment against $4.7BN USD revenue.

Roughly 25% ? so on a gross margin per Titan X card ($400 approx. profit) that means that inside the $400 USD Nvidia spend $90 USD on R&D.

So, minus R&D costs you could then speculate that Nvidia make $390 USD on each Titan X card, assuming my earlier example of a $1000 USD inc. retail price.
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Obviously nvidia is not getting the entire pie! from those 1000$ lets say 18% goes to the etailer, another 15-20% to the brand (AIB)...taxes ... and then leaves nvidia with unit price of around 500-600USD.
 
Found out yesterday my computer struggled for the first time gaming. I had to drop the res in Mortal Kombat X. Do we know what the pricing for these cards are yet? or is it better to get a 970/780ti/980?
 
xLegendary said:
Obviously nvidia is not getting the entire pie! from those 1000$ lets say 18% goes to the etailer, another 15-20% to the brand (AIB)...taxes ... and then leaves nvidia with unit price of around 500-600USD.
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read my post before that one with the breakdown.

I am sure Gibbo would love to make 18% per sale, he would be down Porsche Solihull faster than you could type '992 C2S Powerkit'.
 
Orangey said:
Did anyone know that GDDR5 does not require equal trace lengths?

https://www.micron.com/~/media/docu...note/dram/tned01_gddr5_sgram_introduction.pdf

Not Fiji related I suppose but doesn't deserve its own thread and curious if this is common knowledge.
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Yup, it did originally, spec got updated at some point. I think maybe with the 6970 the requirement changed. Ultimately you get the same effect by staggering the signals. If one trace is 10cm long and takes 10ns for a signal to get across and another trace is 9cm and takes 9ns, the memory controller just delays that second signal by 1ns before it's sent.

it definitely reduced trace length on a pcb and reduced complexity, because when every trace had to be the same length you got all kinds of backwards design routing issues. It likely reduced power somewhat, though you would also add some complexity, die size and power usage in the memory controller to deal with it. Nothing like on the scale of going on package.

Similar to self refresh or whatever the mode is called, fairly certain that was added later on and wasn't possible on the first gddr5 cards.

Common knowledge, probably not, but most people couldn't tell you what makes HBM good or bad, nor what made GDDR5 good or bad. I seem to remember it being mentioned at the time of whichever card it started to be used on, not sure if in general technical info around the launch or in some of the better reviews.
 
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Mtom said:
Interesting stuff (theory) about why fiji won't be a giant chip.
http://forums.anandtech.com/showpost.php?p=37407110&postcount=480
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Makes way way too many assumptions. Either way 550mm^2 compared to 600mm^2 isn't a huge difference and is still absolutely a huge chip.

One of the reasons Hawaii was so good in terms of die size/performance over the 7970 is because the process matured significantly from almost the first products out on it like the 7970 to a significant time later with the 290x. There is only so much saving you get from process maturing. For a new chip on a lower yielding new process you make conservative designs, leaving a little more space(talking another 2-3nm) and maybe throwing in a little more redundancy.

Refreshes of products within a process are usually 5-15% more dense precisely for those reasons, but that is effectively a one time shot, you can't take that 5-15% extra space you left out of the first product for yield reasons more than once.

In terms of the memory controller, there are lots of rumblings, about an HBM memory controller being much more simple and thus smaller... but then it's massively wider. 4096bit vs 512bit is not insignificant. However producing signals that are a magnitude smaller means a lot less logic/components there as well. it's questionable at this point how a 4096bit HBM memory controller will stack up vs a 512bit gddr5 memory controller in size.
 
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Well if people watched the video,David Kanter did mention one of the senior AMD design people,was the opinion of making the GPUs as large as they could,and also mentioned that some of the logic which will not be needed to be used due to HBM,in the past did not scale well with process node shrinks.

He also said,the reason they might be going for an AIO water cooler,was probably less to do with heat,but actually thermal density.
 
drunkenmaster said:
Makes way way too many assumptions. Either way 550mm^2 compared to 600mm^2 isn't a huge difference and is still absolutely a huge chip.

One of the reasons Hawaii was so good in terms of die size/performance over the 7970 is because the process matured significantly from almost the first products out on it like the 7970 to a significant time later with the 290x. There is only so much saving you get from process maturing. For a new chip on a lower yielding new process you make conservative designs, leaving a little more space(talking another 2-3nm) and maybe throwing in a little more redundancy.

Refreshes of products within a process are usually 5-15% more dense precisely for those reasons, but that is effectively a one time shot, you can't take that 5-15% extra space you left out of the first product for yield reasons more than once.

In terms of the memory controller, there are lots of rumblings, about an HBM memory controller being much more simple and thus smaller... but then it's massively wider. 4096bit vs 512bit is not insignificant. However producing signals that are a magnitude smaller means a lot less logic/components there as well. it's questionable at this point how a 4096bit HBM memory controller will stack up vs a 512bit gddr5 memory controller in size.
Click to expand...

Take into account that AMD moved from TSMC to GloFo, and they have a better 28nm node. Supposedly higher clocks,lower voltages, and a bit denser.
 
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