Soldato
Edit double post.
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Possible Radeon 390X / 390 and 380X Spec / Benchmark (do not hotlink images!!!!!!)
- Thread starter Boomstick777
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Caporegime
Looking forward to the real deal next gen, plz no more 28nm. If the spec is legit may well be going back to team red. Just hope they get these out the door on time, if it's late will give Nvidia time to take advantage of market position, and simply drop in products to one up AMD. Although the advantage of that would be cheaper AMD cards, but I would prefer to see AMD lead in performance.
Pretty much set on a 390X for my next card, 20nm + HBM ftw !!
Pretty much set on a 390X for my next card, 20nm + HBM ftw !!
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Developers have zero incentive to release a patch so unless AMD cough up which is about as likely as me winning the lottery nothing will happen.
Caporegime
Your stating facts about things that are nothing more than your own ideas.
Caporegime
While these numbers don't really relate to actual gaming performance, here is a comparison. my R9 290 is overclocked and running at about R9 290X stock performance.
R9 290 OC (2560SP 40C 1.1GHz, 4GB 1.375GHz 512-bit) = 54.05 GB/s
R9 390X (4096SP 64C 1GHz, 4GB 1.25GHz 4096-bit) = 63.6 GB/s [+20%]
Cryptography is integer performance (GPU Core) I don't think Memory bandwidth plays a part in it.
R9 290 OC (2560SP 40C 1.1GHz, 4GB 1.375GHz 512-bit) = 54.05 GB/s
R9 390X (4096SP 64C 1GHz, 4GB 1.25GHz 4096-bit) = 63.6 GB/s [+20%]
Cryptography is integer performance (GPU Core) I don't think Memory bandwidth plays a part in it.
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Caporegime
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Hmmmmm, so the die and memory will be on a single package? I suggest that it will generate a fair bit of heat in that case, maybe that 390X will have a hydro option after all...
(or they'll be radically improving the oem cooler!!)
(or they'll be radically improving the oem cooler!!)
Caporegime
No, other than the IMC (Integrated Memory controller) its not any different to any other GPU, it still has external PCB Memory IC's.
If legit, it must be 20nm as the extra 40% of Stream Processors on the die would make this 615mm^2 in size, compare that with Hawaii at 438mm^2 and GK110 at 550mm^2.
Not a chance, way to big, its 20nm which means a reduction in power consumption.
^^ Plus if it's HBM reduction in power consumption there as well. Now we have weeks / months of waiting with speculation until we finally get some confirmation of specs 
I hope AMD get these out soon..
I hope AMD get these out soon..
Soldato
My wallet is ready two 390s 1440p 144hz display all before May?
two 390s 1440p 144hz display all before May?
Soldato
AMD need to come out and give solid specs ASAP to try and regain some sales percentage I imagine. People might be inclined to save some pennies and not opt for a 970/980 if they look really strong.
Of course, Nvidia would more than likely come right back, but that's what we all want, serious competition at competitive price.
Of course, Nvidia would more than likely come right back, but that's what we all want, serious competition at competitive price.
Soldato
Exciting times a head for sure 
Caporegime
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not really no, the first point is people keep suggesting the OEM cooler is poor because temps were higher and noise CAN be higher while ignoring the die size. Something that is 438mm^2 and puts out 250W is going to get significantly hotter than something that is 550mm^2 and puts out 250W, that is just the way it is. Put the Titan cooler on the 290x and the 290x would have run hotter than the Titan did.
The second point to make is HBM, if it uses it and would be the only situation in which memory was on package, will reduce power usage significantly. IE if a non HBM chip was using 250W, it could be that 30W of that was the actual memory and 40W would be communication between the memory and the gpu.
When you move that on die you cut down the memory power usage to more like 20-25W and the communication power will drop from 40W to like 1-5W. The memory power goes down because you use 1Ghz chips at ridiculous bus width rather than 4Ghz chips on a narrow bus. So lower voltage and much more optimised power usage on the chips themselves. Pushing a signal off package and across maybe 50cm of traces which are say 1mm thick and pushing a signal 1-2 cm across traces that are 20-40nm thick and you have a drop in power usage by a magnitude or more. Both these things are where HBM power savings/performance come from, the ability to massive increase the bus width as the traces become a tiny fraction of the size in silicon as opposed to on a pcb, which allows more speed and reduced frequency for even more power saving. Then the distance from the gpu means massive power savings in actually generating/sending signals back and fourth.
So ultimately bringing memory on package saves more power than it adds by a fairly large margin. Being that most of that communication power is centred in the on die memory controller you're removing 40W there and adding 20W in memory chips.
Seriously, could you just read up on HBM because you just don't seem to get it at all, performance, bandwidth, or how it works fundamentally.
Every GPU since basically their inception has had an integrated memory controller and other than it's design, which changes generation to generation anyway, that will be on die like every other gpu you've bought. Secondly, the entire point of HBM is the memory is on package and not separate and on the PCB. If the memory stacks were on the PCB it would be one, HMC, two, wouldn't offer remotely the same power saving, three, would need to be close to available. It's none of these things.
HBM memory stacks go on the same package as the GPU. The green substrate(usually green, sometimes a brownish/purple colour) is the "package", the chip gets effectively glued onto this package. There are many things with more than one chip on package, Intel's iris pro gpu chips have a large second chip which is cache on the same package, though this afaik isn't quite what AMD is doing. AMD is doing an interposer, which is itself a silicon chip. It's effectively a PCB at the silicon scale, you have a gpu, multiple memory stacks, you put these all down on this silicon pcb which connects too the pads on the chips, then this entire interposer gets stuck to the package, the package goes onto the pcb where the connections to power/pci-e get made.
HBM isn't designed to be stuck on a PCB and CAN'T be stuck on a PCB, it has dense pad connections that can only be connected at the silicon scale. In an area you can fit maybe 50-100 silicon scale connections you can fit maybe 1 or 2 PCB sized trace connections, it's not possible to connect HBM stacks to anything at the PCB level.
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Caporegime
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I happily stand corrected. Will do a wee bit of research before posting rubbish again
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