It was clear from the AMD livestream that their power efficiency claims were smoke and mirrors.
Releasing new chips all with TDPs above 100W and telling us how efficient they are with a reduced 65W TDP was a bit strange.
AMD are forced to follow Intel and push the default settings well above optimal so that performance will look better versus the competition.
I don’t think Z4 is bad, it’s just that Z3 was a difficult act to follow and Intel have finally become more competitive.
Even Papermaster said that Z5 was the one that excited him, so I wasn’t expecting that much.
Whilst Z4 seems decent, with the higher power consumption and temperatures, I am wondering how much of a bottleneck the 3 and 4 nm nodes might be?
It seems as if TSMC will need different techniques rather than just shrinking the current node used here, which they have listed on the roadmap.
I don’t recall what and when or whether it’s too early to say what improvements will come.
Thermal density seems a difficult thing to deal with.