Very crude post.
"Current DDR4-4266 has 19-19-39". Not even really a valid statement, is it? It's binned by GSKILL at these timings with sufficient guardband, it's not any kind of industry standard. JEDEC currently don't offer standards anywhere near those speeds. Moreover, they offer tCAS 17 bins at those frequencies already. Not only that, tCAS and other primary sets aren't the only important timing parameter. Frequency and timings are intrinsically related, it comes down to how close one is able to close in the subset spacing from what MB vendors are setting - and also what the CPU is capable of. If you calculate column access time correctly, you'll notice that for every tCAS jump you need a 266MHz frequency increase to reach the same access time. Not exactly a huge jump in frequency.
What's your point? Do we need DDR5 or not? I say not.