Soldato
Right now I take the word of our Georgian chum.
So I call BS on those charts.
So I call BS on those charts.
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You may be correct regarding the die sizes being different mostly due to the 256/384bit memory interfaces. However, the most expensive Graphics Card component to manufacture is the GPU, followed by the PCB, then VRAM. GPU costs rise significantly with transistor count and PCB costs increase significantly with the number of layers/lanes. VRAM costs I would guess should be quite low due to the general low price of memory modules (you can buy low end cards with 1gb to 2gb of GDDR5 very cheaply).It looks like the GK104 has a similar die size to Tahiti, though maybe smaller, however, the Tahiti die burns up die space for the 384 bit bus. Not pushing the memory controller so hard means that Tahiti uses lower spec RAM modules reducing costs. Also a wider bus reduces the chances of running into irreconcilable bandwidth issues limiting GPU performance.
Degrees of excrement I would think.
I've done a few charts in my time. I did this one when the 7970 launched.
Please note. This picture is a little naughty and definitely not safe for children.
Edit. Actually no, don't want to get in trouble
Degrees of excrement I would think.
Come on guys lets just admit it, we love all this banter before a GPU launch! I've come to genuinely find them quite exciting hah
hahaha i saw that link Total genius this would sale it to the enthusiast market easy
Agreed. I love seeing the speculation and guessing.
Possible GTX660TI card shape:
http://translate.google.com/transla...l=en&u=http://www.arabpcworld.com/?p=6498
Possible GTX660TI card shape:
http://translate.google.com/transla...l=en&u=http://www.arabpcworld.com/?p=6498
Looks nice
The box is the right shape
Fair point... That would certainly allow for more flexibility in tuning the core and shader clocks to their individual limits.
Now that I think about it - wasn't this also the case for the 8800GTX (and related architectures), and also GT200?
edit: Yes it was - see the table towards the bottom of this page: http://www.anandtech.com/show/2549
I wonder if the switch to "shader clock = 2 x core clock" was a compromise to help improve inter-chip communication in Fermi? If the core and shader clocks communicate every clock cycle, internal latencies could be reduced...