Two tightly coupled, "conventional" x86 out-of-order processing engines which AMD internally named module
(i.e., single-module → dual-core, dual-module → quad-core, quad-module → octa-core, etc.) Bulldozer family will lay emphasis on multithreading and multiple cores as well
Up to 8 MB of L3 cache shared among all modules on the same silicon die (16 MB for dual-die MCM), divided into four subcaches of 2 MB each, capable of operating at 2.4 GHz or more at 1.1 V [7]
Native DDR3-1866 memory support [8]
Dual Channel DDR3 integrated memory controller (support for PC3-15000 (DDR3-1866)) for Desktop, Quad Channel DDR3 Integrated Memory Controller (support for PC-12800 (DDR3-1600) and Registered DDR3)[9] for Server/Workstation (New Opteron Valencia and Interlagos)
Cluster Multi-threading (CMT) Technology [10]
Bulldozer module [11][12] consists of the following: up to 2048 kB L2 cache inside each module (shared between the cores in a module)
16 kB four-way L1 data cache (way-predicted) per core and two-way 64 kB L1 instruction cache per module, one way for each of the two cores[13][14][15]
Two dedicated integer cores
- each consists of two ALU and two AGU which are capable for total of 4 independent arithmetic and memory operations per clock per core
- duplicating integer schedulers and execution pipelines offers dedicated hardware to each of two threads which significantly increase performance in multithreaded integer applications
- second integer core increases Bulldozer module die by around 12%, which at chip level adds about 5% of total die space[16]
Two symmetrical 128-bit FMAC (fused multiply-add (FMA) capability) Floating Point Pipelines per module that can be unified into one large 256-bit-wide unit if one of integer cores dispatch AVX instruction and two symmetrical x87/MMX/SSE capable FPPs for backward compatibility with SSE2 non-optimized software
each module has 213 million transistors in an area of 30.9 mm² (including 2 MB L2 cache) on an Orochi die [7]
modules are operating at 0.8 to 1.3 V, achieving clock frequencies of 3.5 GHz or more [7]
11-metal layer 32 nm SOI process with implemented first generation GlobalFoundries' High-K Metal Gate (HKMG)
Turbo Core performance boost to increase clock frequency by 500 MHz with all cores active (for most workloads) and further, as TDP headroom permits [17]
Support for Intel's Advanced Vector Extensions (AVX) instruction set, which supports 256-Bit floating point operations, and SSE4.1, SSE4.2, AES, CLMUL, as well as future 128-bit instruction sets proposed by AMD (XOP, FMA4 and CVT16),[18] which have the same functionality as the SSE5 instruction set formerly proposed by AMD, but with compatibility to the AVX coding scheme.
Hyper Transport Technology rev. 3.1 (3.20 GHz, 6.4 GT/s, 25.6 GB/s, 16-bit uplink/16-bit downlink) [first implemented into HY-D1 revision "Magny-Cours" on the socket G34 Opteron platform in March 2010 and "Lisbon" on the socket C32 Opteron platform in June 2010]
Socket AM3+ (AM3b)
- 942pin, DDR3 support
- will retain backward compatibility with Socket AM3 motherboards (as per motherboard manufacturer choice and if BIOS updates are provided[19][20]), however this will be unsupported by AMD themselves and any such support would be considered "experimental"; AM3+ motherboards will be backward-compatible with AM3 processors[21]. For the server segment, the existing socket G34 (LGA1974) and socket C32 (LGA1207) will be used.
Min-Max power usage - 10–125 watts
Bulldozer Module sharing levels Bulldozer module