So you are an expert on processor microarchitecture now . How did they improve the performance of Alder Lake if its just Skylake cores + small cores bolted on?
It's not the same if the L3 cache has been increased to 30MB for the top model.
Or, do you think Intel has exaggerated IPC improvements? tbf wouldnt be the 1st time.
L3 cache is unifiable. Look at the L1 and L2 that is the individual bit baked into the chip design.
What have Intel shown?