AMD Polaris architecture – GCN 4.0

[pmc25]

If they are low power parts coming first then it could well be Samsung LPP (which GF have licenced so they could be referring to the technology rather than the physical foundry). But they'll be low power, so we aren't talking Fury replacements, but that would explain the comparisons to 950 type GPU's.

But it would also mean basically having two completely different designs on two different processes for their high/mid range parts and their low end low power parts, and taking a big chunk of work away from TSMC isn't exactly going to endear them as customers.

What are you talking about? Polaris is Samsung / GF 14nm LPP only .... and there's going to be practically bugger all on TSMC for AMD, save legacy products. Zen is definitely Samsung / GF.

 

[drunkenmaster]

Low power PER TRANSISTOR doesn't equate to less transistors are possible per chip, they both use 300mm^2 wafers and you can design any realistic chip size you want. There is fundamentally no difference between a 100mm^2 chip and a 600mm^2 chip, take any 25mm^2 section of either chip and it will use (at same clock speed) about the same power. A chip that is three times as large has three times the surface area, it doesn't use more power for an individual transistor nor will it have worse heat production problems. You can make a 600mm^2 chip that gives great performance on a ultra low power variant and a 25mm^2 low overall performance chip on a high performance variant process. They are describing the per transistor characteristics or design goals, it has zero bearing on the max power capable of being drawn or the max chip size possible. IE a chip tuned for lower idle leakage or higher clocks.

The fundamental concept behind making silicon chips in the first place decades ago was someone said hey, if we get these transistors(in the old days literally huge and not in silicon) smaller and closer together they will use less power. Calling a process low power is marketing speak, but not inaccurate. Every single 'performance' variant of a process still used roughly half the power per transistor of the process that proceeded it, every single new process on a lower node is automatically, by design, low power compared to everything that proceeded it. Except now mobile companies are the biggest foundry customers, the names are stupid fabs arguing over how ultra low power they are compared to their competitors megatastically low power process.

There is no difference in equipment or general concepts of a 28nm low power or high performance chip. It's just design rules, if you want to go to 4Ghz you need to have higher voltage and leave 75nm between transistors, if you want to go 500Mhz you can go to X voltage and get the transistors 64nm apart from each other. You can have better or worse transistor designs, ones that work better at lower voltage and leak less at idle or ones that work a bit better but it's all the same process and technology.

AMD aren't making GPUs at TSMC this gen, the name of a process at TSMC or Samsung has zero bearing on the size of overall performance of the chips they make. The individual process name is mostly irrelevant, it's just a set of guidelines for tuning your chip to a given performance area, some chips want less leakage at idle and will be idle more often, others want higher performance, it's still the same process and both AMD/Nvidia are using the higher performance tuned design for the respective foundries processes.

 

[FoxEye]

Look, man. I only need to know one thing: where they are.

And, erm... when I can buy one. OK, I only need to know two things.

 

[Mei]

Roy has put his foot in it so many times, I tend to take what he says with a truck load of salt!

i think sadly no one much belives stuff AMD says anymore
especially the AMD fans lol

we remain eternally hopeful!

i got a good feeling this time ^^;

 

[Orangey]

http://www.techtimes.com/articles/118904/20151224/amd-partners-with-samsung-globalfoundries-to-build-new-14nm-gpu-report.htm

"Because Samsung Electronics and GF have same IP for 14-nano processing, chips that are designed by AMD will all be produced at both factories," a person familiar with the matter tells Electronic Times. "If products are produced from both factories, AMD won't have to worry about a problem regarding lack of supplies."

http://www.techpowerup.com/218578/samsung-to-fab-amd-zen-and-arctic-islands-on-its-14-nm-finfet-node.html

"It has been confirmed that Samsung will be AMD's foundry partner for its next generation GPUs......It gets better - not only will Samsung manufacture AMD's next-gen GPUs, but also its upcoming "Zen" family of CPUs, at least a portion of it. AMD is looking to distribute manufacturing loads between two foundries, Samsung and GlobalFoundries, perhaps to ensure that foundry-level teething trouble doesn't throw its product launch cycle off the rails. "



It could be tho that samsung will make ZEN, and GloFo will make the GPUs

Those are the same article and nothing but wccf-tier assumption parading as fact.

 

[Orangey]

Look, man. I only need to know one thing: where they are.

You're just too bad.

 

[looncraz]

If they are low power parts coming first then it could well be Samsung LPP (which GF have licenced so they could be referring to the technology rather than the physical foundry). But they'll be low power, so we aren't talking Fury replacements, but that would explain the comparisons to 950 type GPU's.

But it would also mean basically having two completely different designs on two different processes for their high/mid range parts and their low end low power parts, and taking a big chunk of work away from TSMC isn't exactly going to endear them as customers.

Polaris 10 is a lower power/performance part. However, it will probably scale to in excess of GTX 960's performance. That means Polaris 10 should be able to occupy somewhere in the $170~$270 price bracket (in a cut-down version and an up-clocked full version - and possibly somewhere in between as well).

Polaris 11 is a higher performance part. No idea where it targets, don't even want to guess - but it'd make the most sense if it targeted 980Ti + 30%. The cut-down version(s) could then target 980 and 980Ti stock performance levels.

As for TSMC, AMD will continue to build Fiji and other GPUs until Polaris has to slip in price or they no longer can generate a profit. Demand for last generation GPUs doesn't cease immediately.

 

[looncraz]

You can make a 600mm^2 chip that gives great performance on a ultra low power variant and a 25mm^2 low overall performance chip on a high performance variant process.

THANK YOU!

Yes, it all comes down to the layer masks and libraries once the process techniques are established. If you have an area of your design that is put under unusual stress (thermal or electrical), you just create a boundary region, reducing density. The libraries will usually have all of this done already for their target applications.

If I want to run my chip at 4GHz on a low power process, all I have to do is design my chip to run at 4GHz on that process

AMD hasn't been doing this with the construction cores - they knew that getting higher frequencies wasn't going to help them enough to warrant the effort, so they removed their high-performance team and put them to work on Zen, and gave the construction cores to their low-power team to save power and increase IPC.

 

[andybird123]

Umkay, so we're building high performance GPU's on a low power process... When both AMD and Nvidia skipped 20nm and decided to do whole new designs on 28nm rather than use a 20nm low power process...

 

[drunkenmaster]

Umkay, so we're building high performance GPU's on a low power process... When both AMD and Nvidia skipped 20nm and decided to do whole new designs on 28nm rather than use a 20nm low power process...

Dear lord.

20nm was planar, planar utterly died at 28nm, there is a reason why Intel went finfet for 22nm and below and why 20nm for TSMC/Samsung blew. EDIT:- more specifically, planar bulk is dead, SOI looks like it has a bit more life in it but SOI/finfet looks like it could be extremely good in a couple of years.

Most process nodes give normally around 1.85-1.95x transistor density and 45-60% reduction in power per transistor, meaning you can roughly double transistor count with the same power usage with each new node.

20nm planar had about 1.9x transistor density and around 20% power drop, the latter is the reason no one used it, it was effectively not a full node(as the industry describes them) drop because it didn't bring one of the two key incredibly important characteristics required from a new node. IT's also worth pointing out that Intel themselves had a massive delay on 14nm due to terrible yields. Double patterning which Samsung/TSMC brought in for 20nm and Intel for 14nm is a huge deal, it's hit all fabs HARD. It caused massive delays, very low yields and much higher costs. A lot of companies would still have gone 20nm even with only 20% power drop because it's not nothing, but yields were just too dire and costs too high to make it worthwhile. Notice those companies that produce commodity chips like Samsung and Apple had no worries about using 20nm for the reasons I pointed out in the previous post. When you care about profit, 20nm costs/yield was non viable.

finfet brought the power down so 20nm finfet(which is what it is), gives overall about a 2x transistor density and a 55-60% power drop over 28nm.


Low power means nothing, the process AMD and Nvidia used for GPUs at 28nm was low power compared to 40nm, would it have worked any differently if the process they used was called low power or high performance? It's just a freaking name, it's the exact same machinery, the exact same process limits, the same smallest lithography, the same fabs, the same production lines. It's a name, the industry has simply shifted to mobile/low power devices so being able to tell your phone customers buying $600 devices that it's made on a new spanking low power node just sounds good.

Every new node realistically gets described as 50% power reduction or 40-50% higher performance, because you can chose to keep same power and up performance or reduce size and power.... reality is most companies choose a mixture of both. If 99% of customers care about more power... call it high power, if 99% of customers care about power saving, call it low power. It's a name, nothing else.

 

[Mauller]

Apparently polaris is starting at around 290X performance to fit the minimum requirements for VR. So small polaris could have 290X performance but at a far lower power envelope.

 

[N19h7m4r3]

Apparently polaris is starting at around 290X performance to fit the minimum requirements for VR. So small polaris could have 290X performance but at a far lower power envelope.

That is going to be exciting if their current 370 or 380 is replaced by something of similar price for 290X performance.

 

[andybird123]

THANK YOU!

Yes, it all comes down to the layer masks and libraries once the process techniques are established. If you have an area of your design that is put under unusual stress (thermal or electrical), you just create a boundary region, reducing density. The libraries will usually have all of this done already for their target applications.

If I want to run my chip at 4GHz on a low power process, all I have to do is design my chip to run at 4GHz on that process

AMD hasn't been doing this with the construction cores - they knew that getting higher frequencies wasn't going to help them enough to warrant the effort, so they removed their high-performance team and put them to work on Zen, and gave the construction cores to their low-power team to save power and increase IPC.

Yes, you can fit a square peg in to a round hole by making the hole much bigger than it needs to be, sounds like a great solution.

 

[drunkenmaster]

Yes, you can fit a square peg in to a round hole by making the hole much bigger than it needs to be, sounds like a great solution.

That isn't what he said at all. It's part of standard chip design, regardless of the process the chip has to be designed for higher speed.

AMD/Anandtech did a piece talking about the memory controller iirc, the 512bit bus with slower memory allowed them to make a smaller denser memory controller than the 384bit bus on the 7970. For Nvidia to get 7+Ghz speeds on their 384bit bus you have to fundamentally design the chip to do so, this means spacing out transistors more and making multiple decisions to allow it to run that high.

Every single chip makes dozens of similar decisions, trade offs or optimisation for every part of the chip, it is a fundamental part of designing chips.

 

[Mauller]

Every single chip makes dozens of similar decisions, trade offs or optimisation for every part of the chip, it is a fundamental part of designing chips.

This is essentially what Nvidia did to get Maxwell 2's power and performance benefits. The chip is cut down to the bare basics for 32bit processing with some of the chips functionality offloaded to drivers.

But the problem with the above is that it made a chip that was very good for gaming but terrible for Compute work. Which is why the quadro maxwell parts are all lower end, leaving the k6000 series as a kepler part.

 

[Mtom]

Those are the same article and nothing but wccf-tier assumption parading as fact.

Well i stay on this side until there's evidence stating that Samsung will NOT be a manufacturer for AMD, just GloFo alone.

 

[FoxEye]

Apparently polaris is starting at around 290X performance to fit the minimum requirements for VR. So small polaris could have 290X performance but at a far lower power envelope.

Source? Small Polaris (P10) is targeting "thin and light" notebooks, and delivers "console class" performance.

We're mostly expecting "middle Polaris" (P11) to be somewhere between 970/390 and 980(ti) +a few %.

If you have a good source for this I'd be very, very surprised. Small Polaris isn't necessarily about performance, it's about power saving. That's why the only demo they've shown to date was geared around the massive power savings vs a GTX 950.

 

[Mauller]

It was brought up in a WCCFtech article but the original source is the speech at VRLA. Go to 16 minutes.


Talking about Minimum VR capable chips in bulk at affordable prices. Which then hints towards 290X level performance for the mainstream.

But it can still be feasible that little polaris has 290x performance and will be used in desktop and portable segments. Just in a portable environment it is down-clocked and down-volted compared to the desktop variant. It essentially makes a very all around chip from a manufacturing cost point of view. But that is all conjecture.

Edit: And i doubt that Bigger polaris will have the performance of a 290X or be sold in that price segment.

 

[FoxEye]

Apparently polaris is starting at around 290X performance to fit the minimum requirements for VR. So small polaris could have 290X performance but at a far lower power envelope.

It was brought up in a WCCFtech article but the original source is the speech at VRLA. Go to 16 minutes.


Talking about Minimum VR capable chips in bulk at affordable prices. Which then hints towards 290X level performance for the mainstream.

But it can still be feasible that little polaris has 290x performance and will be used in desktop and portable segments. Just in a portable environment it is down-clocked and down-volted compared to the desktop variant. It essentially makes a very all around chip from a manufacturing cost point of view. But that is all conjecture.

Edit: And i doubt that Bigger polaris will have the performance of a 290X or be sold in that price segment.

OK I just watched that, and he doesn't say what you think he said.

He said "We can now produce GPUs capable of running VR at a lower cost, higher volume and lower power."

That does not translate - at all - to "our smallest Polaris chip will be capable of running VR".

Those two statements are totally different. One does not even imply the other.

The fact that they can produce chips for VR does not mean that all their chips will be capable of VR.

Everything they actually have said about Polaris 10 - aka small Polaris - is that it is aiming at reducing the power draw in "thin and light" laptops.

I will publicly eat my own underpants if the cheapest and smallest Polaris 10 chip matches a 290X. Or even a 290. It won't happen.

 

[Mauller]

OK I just watched that, and he doesn't say what you think he said.

He said "We can now produce GPUs capable of running VR at a lower cost, higher volume and lower power."

That does not translate - at all - to "our smallest Polaris chip will be capable of running VR".

Those two statements are totally different. One does not even imply the other.

The fact that they can produce chips for VR does not mean that all their chips will be capable of VR.

Everything they actually have said about Polaris 10 - aka small Polaris - is that it is aiming at reducing the power draw in "thin and light" laptops.

I will publicly eat my own underpants if the cheapest and smallest Polaris 10 chip matches a 290X. Or even a 290. It won't happen.

They talk about minimum spec needed for VR being a 290X, then he talks about "We can now produce GPUs capable of running VR at a lower cost, higher volume and lower power."

One can imply the other even thought he did not mention which Polaris he means. it is why i said just conjecture. but i doubt that AMD would make thier bigger polaris chip with just 290X performance. Which then hints towards it being small polaris.

The demo of small polaris was just showing the power saving in a certain performance envelope, not the maximum performance capable of the chip.

So it could be possible that in a desktop environment without the cooling or power restriction of a portable then small polaris could let its legs lose. This is no different to the PS4, the gpu is essentially a 7870 but with less than 7850 performance due to it being under-clocked and down-volted due to the form factor.

And then compare the FuryX to the Fury Nano, the nano since it is downclocked and volted has a massive power saving compared to the FuryX at lower performance etc. Plus we are talking about chips on a new node, so the powersavings could be far better for a certain amount of performance as shown.