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AMD Zen 2 (Ryzen 3000) - *** NO COMPETITOR HINTING ***

Does the PCIE4 mean x470 will not be compatible with 3700x?

3700X will fit in X470 but it won't support PCI4.0 probably.

Why wouldn't it be compatible? Worked 99% of the time if you dropped an Ivy Bridge into a Sandy Bridge motherboard because the PCIE 3.0 controller is on the CPU. I don't see any reason why this would be different, unless there's something insane in the PCIE 4.0 spec that renders existing copper traces electrically incompatible.
 
I know I am going to set people crazy here, but from what I have heard from datacentre workload testing, the performance improvement is closer to 1.4x than 1.25x. All AMD need to do is beat intels per core performance, and dont get greedy on the pricing and they will own the market, charge the same for zen2 as they do for the current chips.
 
LOL I am one who normally points out AMD overhype their products and they usually do.

I was just posting what I was told from a contact who works in a large DC and these guys get pre launch performance data as the vendors try to get orders from them for the new parts, I expect various distributors and possibly retailers may get this sort of data as well.
 
LOL I am one who normally points out AMD overhype their products and they usually do.

I was just posting what I was told from a contact who works in a large DC and these guys get pre launch performance data as the vendors try to get orders from them for the new parts, I expect various distributors and possibly retailers may get this sort of data as well.

I truly believe you. And is something AMD hinted thrice during the head to head benchmark. That the Rome chip was an early unfinished sample.
If that thing can beat the crap out of 2 8180s, which is very mature tech, I wouldn't be surprised the final version been even faster.
 
A closer look:

https://www.anandtech.com/show/13561/amd-previews-epyc-rome-processor-up-to-64-zen-2-cores

amd_rome-678_678x452.png


Two chiplets look smaller than a Ryzen CPU or APU!!

Just quoted you for use of the picture, but something im a bit confused about, there is one controller core in the middle, thats your memory controller, PCI-e etc etc, lets forget about that for now, you are left with 8 chiplets, smaller because of the die shrink (7nm)

If each of those chiplets are 8 core 16 thread each, (making it a total of 64 core 128 thread CPU) who said each chiplet only contains 1 CCX ?

each chiplet can still be 2 x 4 core CCX's stuck together, just smaller and faster because of the die shrink ? who and where does it say its 1 CCX that they've changed to handle 8 cores 16 threads.

anyone confirm this ?
 
Just quoted you for use of the picture, but something im a bit confused about, there is one controller core in the middle, thats your memory controller, PCI-e etc etc, lets forget about that for now, you are left with 8 chiplets, smaller because of the die shrink (7nm)

If each of those chiplets are 8 core 16 thread each, (making it a total of 64 core 128 thread CPU) who said each chiplet only contains 1 CCX ?

each chiplet can still be 2 x 4 core CCX's stuck together, just smaller and faster because of the die shrink ? who and where does it say its 1 CCX that they've changed to handle 8 cores 16 threads.

anyone confirm this ?

Zen 1 consists of 2x 4 core CCX (8 core die)

Each of those chipsets you see on Zen 2 is 2x 8 core CCX (16 core die) 4x 16 core dies = 64 cores
 
Zen 1 consists of 2x 4 core CCX (8 core die)

Each of those chipsets you see on Zen 2 is 2x 8 core CCX (16 core die) 4x 16 core dies = 64 cores

I lost the feed a chunk of the way through - but I don't know if it has been confirmed to be 2 x 8 core CCX or if it is possible we are looking at 4 x 4 core CCX?

I would think that 4 x 4 core CCX would have been a simpler design challenge than 2 x 8.

Not certain it will really make a massive difference either way, it does seem certain that we are looking at 16 cores per chip.
 
I lost the feed a chunk of the way through - but I don't know if it has been confirmed to be 2 x 8 core CCX or if it is possible we are looking at 4 x 4 core CCX?

I would think that 4 x 4 core CCX would have been a simpler design challenge than 2 x 8.

Not certain it will really make a massive difference either way, it does seem certain that we are looking at 16 cores per chip.

Thanks, I don't remember hearing amd mention if each core or chiplet if you prefer is 1 X 8 core ccx, or 2 X 4 core ccx's glued together as Intel puts it, if it is still 2 X 4 core ccx's together to make one 8 core chiplet, then the latency issue between ccx's will remain, maybe a slight reduction due to the die shrink

2 words "mrs" and "gassing" whilst I was trying to watch, the audio wasn't very clear as it was.
 
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From the reading i have done it seems a quite big overhaul of the Zen Uarch, they have improved a lot of the flaws such as Branch Predicition and Front End etc, should be a tastey uplift from Zen+, and if they manage to fit 8 core into a single CCX, that will eliminate a lot of Zens latency issues, also uncoupling the Mem controller from IF will mean better mem speed support etc.

Zen 2 could be quite spectacular.
 
Zen 1 consists of 2x 4 core CCX (8 core die)

Each of those chipsets you see on Zen 2 is 2x 8 core CCX (16 core die) 4x 16 core dies = 64 cores

There are 8x 8c chiplets, not 4x16. The EPYC Gen 1 (32 core CPU's) use 4 dies, with 8 cores per die, with each die containing the two four core CCX's, and all of the I/O. Once EPYC with Zen2 has official specifications, we will find out if the are indeed dual CCX chiplets, or single 8c chiplets which would be a great deal more efficient.
 
There are 8x 8c chiplets, not 4x16. The EPYC Gen 1 (32 core CPU's) use 4 dies, with 8 cores per die, with each die containing the two four core CCX's, and all of the I/O. Once EPYC with Zen2 has official specifications, we will find out if the are indeed dual CCX chiplets, or single 8c chiplets which would be a great deal more efficient.

AMD said "One of the key upgrades for Zen 2 is the doubling of the core density which means we are now looking at 2x the core count for each core complex (CCX)".

So now we have 8 core CCX, and each chiplet is 1 CCX on EPYC Rome
 
AMD said "One of the key upgrades for Zen 2 is the doubling of the core density which means we are now looking at 2x the core count for each core complex (CCX)".

So now we have 8 core CCX, and each chiplet is 1 CCX on EPYC Rome

Do we expect 40-50% (15% IPC + 25% frequency) performance uplift going from the 2700X to a potential 8-core 3700X?! :eek:
 
AMD said "One of the key upgrades for Zen 2 is the doubling of the core density which means we are now looking at 2x the core count for each core complex (CCX)".
Awesome, cheers. I was hoping they were moving to an 8 core ccx. That definitely bodes well for Zen2 on desktop. I wonder if we are going to see 16core mainstream parts or if they are going to go single CCX and higher ipc and clocks.
I get a lot of these upgrades are server specific but if they achieve even close to the IPC improvements we see here on lightly threaded tasks they will be beastly.
I wonder if we are going to see chiplet on desktop... They obviously have not done a shrink of the uncore process yet which surely suggests it.
 
Do we expect 40-50% (15% IPC + 25% frequency) performance uplift going from the 2700X to a potential 8-core 3700X?! :eek:

The IPC performance could be gained from 8 core CCX. As there is latency between the 2 4core CCX as the communication between them works at half ram speed and is dependent to the ram timings also.

And since we are on IPC have a look here, testing 9700K, 2700X, 9900K, 8700K clocked at 4.2ghz with crap ram (3866C18, if it was normal C16 could gain 2-3fps the 2700X)
 
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