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AMD Zen 3 (5000 Series), rumored 17% IPC gain.
- Thread starter AStaley
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Buildzoid got an A520 board of some description to clock ram pretty high - no idea on XMP but even PBO worked. It was a short time after the A520 launched if you want to have a scout through his channel for the info, I didn't pay that much attention to it just remember him saying all forms of overclocking worked
That could have course get overturned in bios updates, pretty sure stuff worked that was specifically mentioned by AMD as not working (such as PBO).
Caporegime
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@Zeed @humbug Look like the dual 6 core CCX of the Ryzen 9 5900 seems to not be a problem in gaming compared with the Ryzen 9 5800X.
A520 looks essentially the same as the B450,but with a BIOS block - wonder if some modders will come up with custom BIOSes?
Buildzoid got an A520 board of some description to clock ram pretty high - no idea on XMP but even PBO worked. It was a short time after the A520 launched if you want to have a scout through his channel for the info, I didn't pay that much attention to it just remember him saying all forms of overclocking worked
That could have course get overturned in bios updates, pretty sure stuff worked that was specifically mentioned by AMD as not working (such as PBO).
A520 looks essentially the same as the B450,but with a BIOS block - wonder if some modders will come up with custom BIOSes?
Yeah, AMD fixed the 'Multi CCD gaming tax' with Zen 2 already, they override Microsoft's idiotic thread scheduling at the hardware level so its not moving the main thread between CCD's.
Well that was OBVIOUS biggest fail of zen2 was AMD doing 2x4 not 1x8 You double dipped on memory latency. That got reduced.. ZEN3 is what I was hoping Zen 2 will be. By removing that bottleneck that is adds to reducing stability of IF and cpu in general due to Temperature looks like Zen3 can take MORE VOLTS and clock higher while remaining stable.
@humbug they fixed what ?? FIXED NOTHING zen 3 shows the ZEN2 FLAW
It was NEVER about THREAD moving shows how little knowledge You got on the matter... It was about extra latency added with trasfering data around 1 chiplet over IO die...
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The problem is the way Microsoft handles threads, they have this 2006 idea that they must balance the load on CPU cores, so the worker threads get randomly moved around, work X on thread 1 is paused and moved to thread 6, stopped again and moved to thread 4, stopped again and moved to thread 8............................................
If the links between your CPU cores is short its not so much a problem, tho its still better if that didn't happen at all, but if you're moving a thread from core 3 CCD1 to core 6 CCD 2 you have to feed it through the memory system all the way around and intro the next CCD, that's what the problem was with multi CCD Zen 1 and gaming.
AMD fixed that with Zen 2 by adding physical hardware that sticks its middle finger up at Microsoft and stops it moving threads around between CCD's.
If the links between your CPU cores is short its not so much a problem, tho its still better if that didn't happen at all, but if you're moving a thread from core 3 CCD1 to core 6 CCD 2 you have to feed it through the memory system all the way around and intro the next CCD, that's what the problem was with multi CCD Zen 1 and gaming.
AMD fixed that with Zen 2 by adding physical hardware that sticks its middle finger up at Microsoft and stops it moving threads around between CCD's.
No its not I got CUSTOM scheduler and i can permamently can asign whatever to whatever I want. Still same problem let me DRAW IT TO YOU if you cant comprehend.
Whatever it is AMD are over-riding Microsoft's stupidity.
ITS NOT MICROSOFT ITS FLAWED DESIGN only stupidity here is from You blaming microsoft for AMD's design decisions.
Do you understand why that design was XXXX now ?? Data inside Chiplet on ZEN2 is jumping over IO DIE not inside Chiplet adds extra latency adds heat reduces stability and so on.
Even if You force software to stik to using selected cores you are still gimped by this design.
ITS NOT MICROSOFT ITS FLAWED DESIGN
Do you understand why that design was XXXX now ??
I'm not death stop shouting.
Its not a "flawed design" is different, it allows AMD to make very scalable CPU's and efficiently, far more so than a monolithic design, every design has its drawbacks, Monolithic CPU's are more limited in scalability than this chiplet design, a good design is one that has its advantages while at the same time mitigates its disadvantages, this is exactly what Zen 2 and Zen 3 does, where are its drawbacks compared with Intel's Monolithic designs?
You see always talking stppid even with draw Yopu dont have a clue what the problem of Zen2 is.... not chiplet design but design of the xxxx chiplet inside moron.
@CAT-THE-FIFTH can You try explain to that chap it more clear than that ?
But that might not be the problem here. If everything is scheduled within a single CCD the 5900X will perform almost as (-MHz/IF) a 5800X those tests might not show CCD-CCD movements. Another point worth keeping in mind is the CCX topology is now 0-1 and 1-2 instead of 2-4.
Thats exacly why Zen3 is good in games lost 34ns of latency inside ciplet.
@benjii no its not its about bad desicion of splitting chiplet's cores to 2x4 instead od 1x8 in Zen2 that was why Zen2 lacked in games but on pair with intel for that god damn 35ns flaw.
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