• Competitor rules

    Please remember that any mention of competitors, hinting at competitors or offering to provide details of competitors will result in an account suspension. The full rules can be found under the 'Terms and Rules' link in the bottom right corner of your screen. Just don't mention competitors in any way, shape or form and you'll be OK.

AMD Zen 3 (5000 Series), rumored 17% IPC gain.

Status
Not open for further replies.
You see always talking stppid even with draw Yopu dont have a clue what the problem of Zen2 is.... not chiplet design but design of the xxxx chiplet inside moron.
bGjxjTu.png
 
Nice paint job Zeed. :)

Although they have fixed the latency issue within the chiplet in Zen 3, where each core in a chiplet can now communicate to each other, without leaving the Chiplet to do so, with the likes of 5900x and 5950x, communication will still need to be transferred via the IO Die when communicating with each chiplet.
In an ideal world, if everything was housed in one chiplet, this would massively reduce latency. Maybe to come in future Zen... (But AMD did say, doing it with chiplets, and separate IO die makes it very cost friendly to mix and match new chiplets to test new vs old architectures on the same piece of silicone.
 
Last edited:
Anyone know if per core overclocking works on these chips?.

You could do it on Zen 2 with ryzen master but would cause some cores to just sit at base clock speed.
 
@mikeym @LtMatt gotta love informing idiots when they got no clue what they are talking about :)

@true_gamer added more so maybe with 1 brain cell he can comprehend difference between xen 2 and zen3 chiplets and where performance actuially came from and why its not as massive jump in multithread from zen2
xfa3s22.png
 
Thats exacly why Zen3 is good in
ITS NOT MICROSOFT ITS FLAWED DESIGN only stupidity here is from You blaming microsoft for AMD's design decisions.
0CQiBXE.png


Do you understand why that design was XXXX now ?? Data inside Chiplet on ZEN2 is jumping over IO DIE not inside Chiplet adds extra latency adds heat reduces stability and so on.
Even if You force software to stik to using selected cores you are still gimped by this design.

Stupid like a fox maybe. TBH bolting clusters of 4 cores together over IF is also a stroke of genius. The alternative is a ring system and we have seen how that scales.
 
Anyone know if per core overclocking works on these chips?.

You could do it on Zen 2 with ryzen master but would cause some cores to just sit at base clock speed.
Hard to say man think it will be die aka all 8 cores some are hitting 5ghz on 5900x
 
@mikeym @LtMatt gotta love informing idiots when they got no clue what they are talking about :)

@true_gamer added more so maybe with 1 brain cell he can comprehend difference between xen 2 and zen3 chiplets and where performance actuially came from and why its not as massive jump in multithread from zen2

Calm down Zeed, no need to go around calling anyone morons or idiots.
 
@Zeed Instead of drawing diagrams of what we all already know try actually explaining the reasoning behind your blanket statements. That would be the clever thing to do...
 
@mikeym @LtMatt gotta love informing idiots when they got no clue what they are talking about :)

@true_gamer added more so maybe with 1 brain cell he can comprehend difference between xen 2 and zen3 chiplets and where performance actuially came from and why its not as massive jump in multithread from zen2
xfa3s22.png

This is wrong.

The CCD on Zen 2 has 2 quad-core CCX which talk to each other via the IF structure on their CCD, and not via the IO die which sits independently nearby:

https://hexus.net/tech/news/cpu/131549-the-architecture-behind-amds-zen-2-ryzen-3000-cpus/

 
Status
Not open for further replies.
Back
Top Bottom