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AMD Zen 5 rumours

humbug said:
Difficult to know.

You're right the article doesn't talk about IPC, and yet the slide does, but it also qualifies that with (1T) its as if it the slide was made by someone who doesn't understand what IPC is, qualifying threads is irrelevant when quoting IPC, you would only do that if you were including clock speeds which are usually different 1T to nT.
Some people use IPC and clock speeds interchangeably, which is idiotic, they have no understanding of it.... given the poor quality of todays tech journalists i'm going to assume they are idiots and agree its probably a combilation of clock speed and IPC.

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IPC has seemed to become a bit of a "buzzword" these last couple of years, ever since Ryzen came out and AMD were going on about the increase in performance because of it. And people have just seemed to jump on the word without fully knowing what it means.

It seems pretty unlikely though that we get 22-30% IPC gains on top of the gains from 3nm. That would put the overall uplift at some pretty insane levels, and quite frankly I dont think thats possible unless a lot is coming from the cache and their X3D chips become the norm, getting rid of the regular chips and just using the 3D V-Cache tech across the board
 
Capitano said:
IPC has seemed to become a bit of a "buzzword" these last couple of years, ever since Ryzen came out and AMD were going on about the increase in performance because of it. And people have just seemed to jump on the word without fully knowing what it means.

It seems pretty unlikely though that we get 22-30% IPC gains on top of the gains from 3nm. That would put the overall uplift at some pretty insane levels, and quite frankly I dont think thats possible unless a lot is coming from the cache and their X3D chips become the norm, getting rid of the regular chips and just using the 3D V-Cache tech across the board
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Yes, i think i agree with all of that.

On an added note i miss the days when tech journalists were proper nerds and not just Youtube savi, because they understood what they were talking about you knew exactly what they were talking about, there was never any missunderstanding.

IPC is not clock speed and clock speed is not IPC, one is how much work the CPU can do for every cycle, the other is how many cycles its doing per second.
 
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Grim5 said:
If zen5 is 3nm it 100% ain't coming this year cause Apple owns 100% of all 3nm wafer supply for all of 2023
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Except we know that orders by a lot were cut on the backdrop of lower demand and forcasts over last 6 months so maybe there will be stock available now for such. Although I am still expecting a 2024 release tbh unless there a huge push because of expected Intel pushes.
 
In defense of RedGamingTech, he did first say that Zen5 clock speed is not expected to change relative to Zen4, so that makes any performance gained pretty much come from IPC improvement.
As for 1T IPC being same as MT IPC, sometimes depends on not being starved for memory bandwidth
 
Zen5 might use TSMC 4NM? The Zen4 APUs are made on TSMC 4NM,so a lot of work has already been done testing out the process node. It also could explain Zen5 appearing a bit earlier than people expected.
 
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alec said:
In defense of RedGamingTech, he did first say that Zen5 clock speed is not expected to change relative to Zen4, so that makes any performance gained pretty much come from IPC improvement.
As for 1T IPC being same as MT IPC, sometimes depends on not being starved for memory bandwidth
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That would be a huge jump, tho not impossible, Zen 2 to Zen 3 was >19%.

The "Significantly Larger L1 Cache" will contribute given that 3nm is significantly smaller than 5nm and therefore wouldn't increase read / write latency.

The thing that i do find interesting is the unified L2 Cache, Bulldozer (Yes i know) had Unified L2 per 2 cores, it could dynamically operate in either 512KB per 1 core in each 2 core cluster for MT or one single 1MB L2 to make the two cores one big one, very interesting and innovative design where for MT workloads you would have 8 individual cores or for 1T workloads you would have the joining of two cores to make one big one.

The problem is the Windows scheduler was confused by it, it never worked, it was always just one of 8 cores. So the big single core was never a thing.

I'd be interested to know why AMD are going back to a similar design.
 
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humbug said:
That would be a huge jump, tho not impossible, Zen 2 to Zen 3 was >19%.

The "Significantly Larger L1 Cache" will contribute given that 3nm is significantly smaller than 5nm and therefore wouldn't increase read / write latency.

The thing that i do find interesting is the unified L2 Cache, Bulldozer (Yes i know) had Unified L2 per 2 cores, it could dynamically operate in either 512KB per 1 core in each 2 core cluster for MT or one single 1MB L2 to make the two cores one big one, very interesting and innovative design where for MT workloads you would have 8 individual cores or for 1T workloads would you have the joining of two cores to make one big one.

The problem is the Windows scheduler was confused by it, it never worked, it was always just one of 8 cores. So the big single core was never a thing.

I'd be interested to know why AMD are going back to a similar design.
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Oh i should add that Mike Clark, AMD's chief CPU architect was the architect for both Bulldozer and Zen, all of them.... how interesting.
 
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humbug said:
Yes, i think i agree with all of that.

On an added note i miss the days when tech journalists were proper nerds and not just Youtube savi, because they understood what they were talking about you knew exactly what they were talking about, there was never any missunderstanding.

IPC is not clock speed and clock speed is not IPC, one is how much work the CPU can do for every cycle, the other is how many cycles its doing per second.
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Me too, youtube and other social media platforms has given too many idiots a platform in recent years (common knowledge I know)

Back in the day when you read an article or even on youtube when you saw a tech video from years ago, you knew that the person knew what they were talking about. Nowadays you need to research into a person to see if they even have the credentials
 
Zen 5 info

Seems AMD is doing quite a lot of market segmentation this time.

Servers get zen5 and on TSMC 3nm with up to 192 core counts and lots of ddr5 channels.

Laptops gets zen5c which has big.little architecture on 3nm and up to 24 cores.

Desktop however gets the bottom of the stick; AMD is feeling the heat from Intel on price and AMD can't afford to use 3nm as it's too expensive. So ryzen 8000 gets 4nm with max core count of 16 cores again. Main improvements is 15%-25% IPC and tiny clock speed bump, small improvement to I/O and memory controller for DDR5 6400. In terms of performance this is expected to be the same as Zen 2 to Zen 3. Zen5 doesn't launch with 3D v cache, AMD will launch seperate models again

 
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Grim5 said:
Jim Keller shows off Zen 5 performance numbers. He also shows off other unreleased products but unlike those he doesn't say his numbers are estimates


The summary from Kepler's slides is that he says Zen 5 runs slightly higher clock speeds than Zen 4 and has 23% higher IPC


www.pcgamer.com

AMD's Zen 5 CPU is scary fast according to performance numbers from the actual father of Zen

Jim Keller details Zen 5's performance and it's looking like a beast.
www.pcgamer.com www.pcgamer.com
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Its going to be a beast....

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humbug said:
Its going to be a beast....

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Well I know the server products are going to be beasts because they are getting more cores, more cache and will be on TSMC 3NM. But desktop is up in the air and will be on 4nm not 3nm. Though 23% IPC and slightly higher clocks is nothing to sniff at and I'll still upgrade for that but I may decide to wait for the X3D models this time
 
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With TSMC talking about having a surplus of 7/6nm production availability a last hurrah for AM4 with 6nm Zen3+ models would offer a nice upgrade path to the masses of people still on AM4. Releasing Zen3+ APUs on the desktop with RDNA2 would also be nice.
 
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