Did some testing to CLDO_VDDP, doesn't seem to do anything if I set it higher than 0.9v at 3600Mhz and according to the Stilt raising it is only useful if going for clocks higher than 3600Mhz on the memory.
So if going for 3733Mhz raise it to 1v, if not just leave it auto (0.9v).
VDDG can probably be left on 0.95v/auto for 1800Mhz Fabric Clock, albeit setting it to 1~1.05v probably won't hurt and is needed for higher clocks.
Edit: Did some VDDG testing too, 0.95v to 1.05v had no effect on stability with the Fabric at 1800Mhz, but it had a very minor effect on memory read/copy of <1% (~51400MB/s read/~52000MB/s copy with 0.95v vs ~51900MB/s read/~52300MB/s copy with 1.05v). Might as well do 1.05v VDDG since I didn't notice any drawbacks other than losing minor power savings.
So if going for 3733Mhz raise it to 1v, if not just leave it auto (0.9v).
VDDG can probably be left on 0.95v/auto for 1800Mhz Fabric Clock, albeit setting it to 1~1.05v probably won't hurt and is needed for higher clocks.
Edit: Did some VDDG testing too, 0.95v to 1.05v had no effect on stability with the Fabric at 1800Mhz, but it had a very minor effect on memory read/copy of <1% (~51400MB/s read/~52000MB/s copy with 0.95v vs ~51900MB/s read/~52300MB/s copy with 1.05v). Might as well do 1.05v VDDG since I didn't notice any drawbacks other than losing minor power savings.
Last edited: