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Wasn't development on 10nm and 7nm running at the same time independent of one another? Meaning if 10nm is scrapped or delayed it doesn't have an immediate knock on effect on 7nm.
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Intel kills 10nm ?? oO
- Thread starter Zeed
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if they're scrapping it then it means they'll likely go for 7nm, not carry on sticking with 14nm because that would be so stupid
Soldato
Intel's 10nm was (favourably iirc) comparable to normal 7nm from companies like TSMC and Samsung anyway so their own 7nm would probably be similar to other company having 5nm.
Soldato
It doesn't work like that. Intel's next node the 7nm EUV is the same at TSMC & Samsung's.
Soldato
The process size of Intels 10nm is not far off the same dimensions as TSMC and Samsung.
https://www.semiwiki.com/forum/content/7602-semicon-west-intel-10nm-gf-7nm-update.html
This shows what I mean.
Soldato
Yet is the case for 10nm. Not 7nm euv
Soldato
Can you show anything proving this? I haven't seen any real technical info on Intels 7nm EUV.
7nm EUV should be double the density of their 10nm delayed process.
But there are other problems: https://www.anandtech.com/show/13683/intel-euvenabled-7nm-process-tech-is-on-track
According to ASML, one EUV layer requires one EUV step-and-scan system for every ~45,000 wafer starts per month. Therefore, if Intel plans to use EUVL extensively for 10 to 20 layers, it will require approximately 20 to 40 EUVL scanners for a fab with a 100,000 wafer starts per month capacity. Considering that Intel is not the only company with plans to use EUVL in the 2020s, getting the number of EUVL scanners it might need for HVM at multiple fabs may be a challenge.
I doubt that aspect will be a problem as Intel has been working on 7nm awhile - they haven't transitioned from 10nm to 7nm as both ran side by side.
You don't understand that everything depends on ASML and if ASML say they will not deliver the required systems to intel for mass production, then intel will produce some things only in limited quantities. Otherwise, yeah, intel can work on their part as much as they like.
Also, it is clearly stated 2020s... so won't be anytime soon.
It isn't ASML who said that. Intel have enough scanners to get started (unlike TSMC they lead their 7nm process with EUV in mind) and ramping up the rest through 2019 when they and Samsung get another ~20 scanners each.
EDIT: I'm not saying Intel will be ready before 2020s but this is a lot of the reason GF dropped from the 7nm race and TSMC went with double patterning for their first 7nm process - Intel and Samsung have had the lion share of equipment.
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Associate
Its all very like when Intel were having issues with 90nm back in the Prescott P4 days. Back then they transitioned to 90nm but it performed worse than 130nm which Northwood was made on. The process was hot, leaky and gave poor yields. That lead to them essentially jumping to 65nm which proved to be a much better process. They were ahead process wise back then but in a bit of a hole against AMDs Athlon 64.
In the past when under pressure they've always pulled something out of their hat. I wonder if 7nm and Sunny Cove will be now what 65nm and Conroe was back then?
In the past when under pressure they've always pulled something out of their hat. I wonder if 7nm and Sunny Cove will be now what 65nm and Conroe was back then?
They seem to be turning to the Israelis again - which is what they did the last two times they needed to pull something out of the hat (with amongst other things a proposed 11bn new fab there).
I doubt it.
GlobalFoundries dropped from all future races, starting with what is a 10nm intel equivalent. The same process intel can't produce anything in meaningful quantities, and 10nm is many times an easier process to deal with.
Intel has been working on 7nm w/ EUV separately for almost 20 years at a technical level what has been a stumbling block for their 10nm is an irrelevant issue to their 7nm. The management issues are another matter though.
I think you are misunderstanding the issue here.
Ok, let it be like you say, the problem that comes and you ignore is physics and all quantum effects that will come into play once the transistor gets that small. intel won't fix anything, even if you give them 100 years.
I'm not sure what you are saying, seems a touch petulant. Intel pushed their 10nm too far trying to get a 3 year jump on the competition which ended up more like 3 years behind - though the overall process is more relaxed some aspects they pushed out the boat and it just didn't work out without EUV and there is only so far you can relax that process and you might as well just do another optimisation pass on your 14nm and move on to a proper sub 10nm process. The technical problems that have plagued their 10nm aren't a factor in their 7nm - they haven't been developing 7nm as a continuation of their 10nm which is the assumption that many people have in the back of their minds - their 7nm development has been ongoing alongside their 10nm for years and while some lessons will have been learnt it isn't dependant on the success or failure of their 10nm.
Thought I would chip in on this, Intel hasn't cancelled 10nm... these rumors have been created by the media.
Intel's validation is what holds the mass production part back, what other foundries say is OK isn't OK for Intel as the validation spec is extremely aggressive... the first parts to roll off are server grade so need to qualify to the server validation spec.
Process development all happens in parallel, there are no separate nodes or tech, once a process matures the knowledge and techniques are absorbed into the next node, any new updates improvements are also put back into older nodes further fine-tuning and improving it, its an iterative process.
As for EUV its only a tool, its not a deciding factor whether a process will work or not, it merely reduces the use of multi-patterning which cranks up your yield.
You also need to remember, reliability falls pretty fast after 10nm, you have to add a ton of transistors/circuitry/logic blocks to counter-act that, that "density" which is promised at sub 10nm simply disappears... and now you have massive leakage/static power to also worry about.
Comparing to other foundries its more or less like this, ignoring leakage, power etc... for the sake of comparison. Keep in mind each foundry also measures slightly differently, you cant do a 1:1 comparison, they have done this intentionally.
Intel 14nm++ is equivalent in density to all the other 10nm nodes.
Intel 10nm is is equivalent in density to all the other 7nm nodes.
Intel 7nm is equivalent in density to all the other 3-5nm (approx) nodes.
Intel's validation is what holds the mass production part back, what other foundries say is OK isn't OK for Intel as the validation spec is extremely aggressive... the first parts to roll off are server grade so need to qualify to the server validation spec.
Process development all happens in parallel, there are no separate nodes or tech, once a process matures the knowledge and techniques are absorbed into the next node, any new updates improvements are also put back into older nodes further fine-tuning and improving it, its an iterative process.
As for EUV its only a tool, its not a deciding factor whether a process will work or not, it merely reduces the use of multi-patterning which cranks up your yield.
You also need to remember, reliability falls pretty fast after 10nm, you have to add a ton of transistors/circuitry/logic blocks to counter-act that, that "density" which is promised at sub 10nm simply disappears... and now you have massive leakage/static power to also worry about.
Comparing to other foundries its more or less like this, ignoring leakage, power etc... for the sake of comparison. Keep in mind each foundry also measures slightly differently, you cant do a 1:1 comparison, they have done this intentionally.
Intel 14nm++ is equivalent in density to all the other 10nm nodes.
Intel 10nm is is equivalent in density to all the other 7nm nodes.
Intel 7nm is equivalent in density to all the other 3-5nm (approx) nodes.
You can only go so far though before the success rate using just multi-patterning is so low it is essentially a failure so it is effectively a deciding factor on whether a process will work (as in commercially viable) or not.