Deleted member 66701
Deleted member 66701
Makes me wonder how they will enforce distinction between TR and Epyc when they are happy to stack cores on the consumer part.
EPYC is 8 channel mem and TR is only 4 channel, meaning on 24 and 32 core TR two cores will have no direct access to memory and will have to go through the infinity fabric. This will increase memory latencies and will affect applications sensitive to that (i.e. database systems - one of EPYCs main markets). Shouldn't affect typical HEDT type workloads such as video and 3D rendering. That's the differentiation between EPYC and TR.
Looking forward to dropping a 32 core into my system in August

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