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NVIDIA RTX 50 SERIES - Technical/General Discussion

Don’t deflect - take responsibility for how you engage with others. In this case, you got a duly curt response because you have responded with a dismissive tone after not reading (or comprehending, but I expect not reading) what I had quoted… and seemingly ignoring the rest of my post in which I summarised additional conflicting info concluding that (i) it’s not clear and (ii) whatever the position is we all need it clarifying.
What are you talking about, the only deflection going on here is from you with your tone policing.
I can’t offer anything more specific than that but it quite clearly suggests, truthfully or not, that there have been changes to their ‘new cables’.
Right so no changes then, just the usual attempt from the sycophants to blame anyone other than the company with the world largest market cap that designed the appliance that's drawing the power. :rolleyes:
 
Right so no changes then

It literally (!) says the new cables have “enhanced terminal and connector housing materials, along with thicker wires.”

:confused:

Tbh I’m lost as to how you can read that (repeatedly?) and remain of the view that there have definitely been no changes after the make of the cable has come out said there have been changes. My own position is simply that it’s confusing; most info available suggests that there have been no changes, yet this suggests the opposite.

Sorry to others for continuing this. I’m not sure there is anything left to say now.
 
I still think the root cause of this issue is that the connector is designed within an inch of it's life.

It's a multistage failure. It's what happens when you have cascading system design failure points with no backups.

Step 1) design a connector that cannot handle more than 100watts on each of its 6 wires and then make a GPU that needs 600w, so that if even a single pin is not making full contact or a single wire is damaged the entire thing is now overloaded.

Step 2) design VRM power delivery so that the GPU has no way to balance current draw across the 6 wires and no way to detect unbalanced current, so that when the connection fails and overloads, the GPU and PSU cannot shutdown and will have a meltdown
 
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From DerBauer's video, I don't think it's necessarily the connector.
Some 12V wires carrying in excess of 20 amps while the others are down around the 5A mark is a huge issue. Something somewhere's not balancing the load.

If the 12HPWR spec is for 650 watts, that's 54 amps split across 6 cables - so max 9 amps per cable. Running double or triple on one conductor that IS going to melt something.
 
From DerBauer's video, I don't think it's necessarily the connector.
Some 12V wires carrying in excess of 20 amps while the others are down around the 5A mark is a huge issue. Something somewhere's not balancing the load.

The GPU cannot balance the power; the VRM design of the 5090 and 4090 does not allow for power balancing, if one wire does 20amps, regardless of the reason why, there is no way to stop it and you have run away thermal meltdown
 
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The GPU cannot balance the power; the VRM design of the 5090 and 4090 does not allow for power balancing
So what, was the PSU providing unbalanced power?

You'd think there'd be a bus type connection across each end of the cable for the 12V pins and the ground pins. Or similar in the PSU and GPU connectors.
 
So what, was the PSU providing unbalanced power?

You'd think there'd be a bus type connection across each end of the cable for the 12V pins and the ground pins. Or similar in the PSU and GPU connectors.
The buildzoid video gives a good breakdown of the problem. The power supply has no control, it never has.
 
From DerBauer's video, I don't think it's necessarily the connector.
Some 12V wires carrying in excess of 20 amps while the others are down around the 5A mark is a huge issue. Something somewhere's not balancing the load.

If the 12HPWR spec is for 650 watts, that's 54 amps split across 6 cables - so max 9 amps per cable. Running double or triple on one conductor that IS going to melt something.
Specifically, nothing anywhere is balancing the load. Should have been part of the spec for the PSU side to load balance, or at least for the 4000 and 5000 series cards to have 3+ shunt resistors to load balance there.

As it is, the best we can do is to use 3+ 8-pin connectors on the PSU side rather than the 12VHPWR PSU connector, as those will at least be power draw capped.
 
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Genuine question - if the Asus software can monitor the amperage down each core of the cable, then doesn't that mean there is some scope for safety measures? Or am I misunderstanding?
 
Genuine question - if the Asus software can monitor the amperage down each core of the cable, then doesn't that mean there is some scope for safety measures? Or am I misunderstanding?
Just based on the buildzoid video, they have a whole complicated extra bit of stuff between the connector and the rest of the card. So it's specific to thier card, and as far as I can see all it can do is switch itself off if it detects something screwy
 
Genuine question - if the Asus software can monitor the amperage down each core of the cable, then doesn't that mean there is some scope for safety measures? Or am I misunderstanding?
It's just that though - software. It will alert you, but that's about it - no kill switch.
 
Specifically, nothing anywhere is balancing the load. Should have been part of the spec for the PSU side to load balance, or at least for the 4000 and 5000 series cards to have 3+ shunt resistors to load balance there.
You can't expect the PSU to do the load balancing because it has no knowledge of what's been connected to it, things that use electricity draw power.
 
Just based on the buildzoid video, they have a whole complicated extra bit of stuff between the connector and the rest of the card. So it's specific to thier card, and as far as I can see all it can do is switch itself off if it detects something screwy
Yeah derBauer mentioned this. The FE cards seem to have some form of bus on the 12vHPWR whereas the Asus card has separate circuitry for each wire.
 
You can't expect the PSU to do the load balancing because it has no knowledge of what's been connected to it, things that use electricity draw power.
If as mentioned the FE has a bus on the card side, then the PSU is definitely doing something wrong ...? I mean these cables should naturally load balance, as a conductor heats up its resistance increases relative to the other conductors and as such it should carry less current.
 
In most electric circuits you use a fuse to protect the cable. There is no point playing a merry go round of blaming each side of the components when its a free mix bag. They should have this covered when they meet for these standards and embark on a new method/design.
 
If as mentioned the FE has a bus on the card side
Not sure what you mean when you say "bus" as those are normally used in communications, do you mean busbar?

Also while there is some resistance drop when a conductor heats up you're talking about pretty small changes, maybe the 10% 'ish range by going from room temp to 100°C, the same sort of range you'd see from using a 6' wire instead of a 3' wire.
 
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The simple answer would be just to go back to the drawing board and make a bigger connector based on the 8 Pin PCI-E. At least it was proven, plugs in properly, and was massively overrated.

Each pin on the "old" connector is rated for 8A*12V = 96Watts, but is de-rated to 50Watts for a bigger safety margin.
Make a 20 pin connector (9x12V, 9xGND, and a couple of spare pins for sense), 9x12V pins = 864Watts. De-rate it a bit and you'd still be good for 600Watts (and still with more safety margin than the current fire hazard which is 600W but with a maximum of only 684W!)

It wouldn't take up much more space than 2x 8 pin connectors, as you wouldn't have the space between them
 
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It's bizarre that they can design a gpu with 92 billion transistors but seem to be incapable of designing a lead with 16 cables and a plastic plug at each end. You'd think some basic electrical engineering would be a simple task compared to chip design.
 
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