It's not a question if AMD is big enough to make huge chips. There is a lot more to it than that, as you well know. If huge monolithic chips were the future, do you think that Intel would be striving their nuts off to get their chipletts out of the door.
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Poll: Ryzen 7950X3D, 7900X3D, 7800X3D
- Thread starter kindai
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Now here is a good point, Intel have for the past 4 years trying its hardest to copy exactly what AMD are doing.
I don't know i don't follow what Apple are doing, i don't mean that in a derogatory way i'm sure its all very interesting but i have my plate full with hobby interests already.
Pretty much all semi conductor companies have been trying to do MCM and 3D stacking for decades because they all recognise and have done for decades the limitations of monolithic. Apple are no different.
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M2 Max is almost a wafer-scale chips with the way it is arranged. Think Cerebras - https://en.wikipedia.org/wiki/Cerebras#Technology - although no images on the wiki article but found one:
What hasn't been tried AFAIK is designing a chip can be cut up but can also be used as one piece. Yes, the traces would have to big and all heading out to the next "chiplet" and when cut the connections would have to be routed under the chip somehow.
On the other hand 3D stacking is sort of like that. So maybe in Zen5 or so, the IO die will no longer be beside the CCD but underneath it as every mm costs hugely in power.
What hasn't been tried AFAIK is designing a chip can be cut up but can also be used as one piece. Yes, the traces would have to big and all heading out to the next "chiplet" and when cut the connections would have to be routed under the chip somehow.
On the other hand 3D stacking is sort of like that. So maybe in Zen5 or so, the IO die will no longer be beside the CCD but underneath it as every mm costs hugely in power.
Soldato
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I don't think its possible to remove previous drivers I couldn't find an option to do so and read somewhere else you shouldn't anyway. The new ones installed over the old ones fine
That is interesting.M2 Max is almost a wafer-scale chips with the way it is arranged. Think Cerebras - https://en.wikipedia.org/wiki/Cerebras#Technology - although no images on the wiki article but found one:
What hasn't been tried AFAIK is designing a chip can be cut up but can also be used as one piece. Yes, the traces would have to big and all heading out to the next "chiplet" and when cut the connections would have to be routed under the chip somehow.
On the other hand 3D stacking is sort of like that. So maybe in Zen5 or so, the IO die will no longer be beside the CCD but underneath it as every mm costs hugely in power.
They would need an interposer under that, a piece of silicon inside the PCB with the traces to connect it all together, Ryzen and RDNA3 chips all sit on top of an interposer.
Of course its not a simple as that, actually making it work is the complicated bit.
While making this one foot die work might be theoretically possible actually doing it is an entirely different matter and even if they could the package is way too large to actually use.
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It’s done through windows apps AFAIK. Just read that it can cause conflicts. Most people I’ve asked say they just leave it to be fair.
You hit scaling and cost walls with those types of architecture and the result is underperforming expensive chips, that’s only remedy is push power use to gain performance.
If the goal is to build slow, expensive and power hungry chips, those types of designs are great, but without silicon stacking or some technological breakthroughs, you run into a dead end like Intel.
I can think of one company that builds the end game of monolithic designs and it’s power use is measured in the kilowatts range.
@KompuKare on 3D stacking.
These 3D chips are showing us where AMD are going next with APU's.
The 7000 has a token iGPU, its just for display out put, nothing more, on the X3D variants it has access to the 3D stacked cache, which is even on a different die. the result...
A 3.3X improvement in performance.
It didn't need access to that cache and i'm sure it needs to be wired so to do it....
These 3D chips are showing us where AMD are going next with APU's.
The 7000 has a token iGPU, its just for display out put, nothing more, on the X3D variants it has access to the 3D stacked cache, which is even on a different die. the result...
A 3.3X improvement in performance.
It didn't need access to that cache and i'm sure it needs to be wired so to do it....
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As I'm watching him abit more his content is no real different to the attention seeking, clickbaiting, trolling and fanboying that goes on here.
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The link for that ^^^ sorry.
AMD Ryzen 7000 "Phoenix" APUs with RDNA3 Graphics to Rock Large 3D V-Cache
AMD's next-generation Ryzen 7000-series "Phoenix" mobile processors are all the rage these days. Bound for 2023, these chips feature a powerful iGPU based on the RDNA3 graphics architecture, with performance allegedly rivaling that of a GeForce RTX 3060 Laptop GPU—a popular performance-segment...
What a night, first Geordie Shore, then lame chasers and a finale of Jersey Shore. Totally reem.As I'm watching him abit more his content is no real different to the attention seeking, clickbaiting, trolling and fanboying that goes on here.
That's not true, not by a long shot. At same wattages, rpl is 10-15% less efficient than zen 4 at heavy mt. But on the other hand it wins massively in lower threaded tasks like the whole Adobe suite.
The biggest problem with the 13900k is gaming efficiency which sucks, and it is why I abandoned it for the 12900k.
Regards the 7900x3d, they should have just made a 7600x3d. Although I appreciate it’s probably got less profit margin for them.
I wonder if we will see the next generation of x3d chips go a different route, perhaps 3D cache on all cores/chiplets.
This current design has some benefits clearly but it seems a bit inelegant design wise.
I wonder if we will see the next generation of x3d chips go a different route, perhaps 3D cache on all cores/chiplets.
This current design has some benefits clearly but it seems a bit inelegant design wise.
I think the chance of a 5600X3D is possible. Maybe once AMD have enough salvaged parts to release it as a temporary product.
Still dodging the questions.
1) Do you think a monolithic implimentation of AMD's current architecture perform worse?
Or
2) Do you think better performance is going backwards?
I know the chipplet approach helps with yields and costs. That's why I didn't ask that question.
Saying that going monolithic would be going "backwards" sounds more like a fanboy defending his team's current approach rather than a defendable assertion.
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