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** The Official Nvidia GeForce 'Pascal' Thread - for general gossip and discussions **

I get the feeling they are now waiting for VR and the inevitability of people being frustrated with their 6/7xx cards and upgrading to 9xx.
Then they'll release the new ones to double milk.

Pure theorycraft, but I feel like I've waited an age with this 980 and if it doesn't perform well enough, and Pascal is gonna be far off, I may end up plumping for a 980 ti in the meantime.
 
Worst case you keep an eye on the news and sell at first sight of new cards...

with any luck you get a golden chip and recoup more than your outlay with the right buyer.
 
http://www.techspot.com/news/63436-nvidia-pascal-gp104-gpu-gddr5-hbm.html

A recent shipment of what appears to be Nvidia's upcoming Pascal GPU from Taiwan to Bangalore has revealed some possible information about the chip before its launch later this year.
The shipment information suggests that Nvidia's GP104 Pascal GPU will be 37.5 x 37.5 mm and will feature 2,152 pins. While there's no firm information to confirm such a move, the surprisingly small die size indicates Nvidia will not use high-bandwidth memory (HBM) along with this GPU.
The reason why it appears Nvidia will not use HBM with the GP104 is that a die of this size could not accommodate both a high-performance GPU and the HBM chips, which sit on the same substrate. Instead, current speculation suggests GP104 graphics cards will use GDDR5 or GDDR5X, resulting in less memory bandwidth than a HBM solution.
Click to expand...

Not surprised to read this and it was mentioned long ago that Nvidia would be using GDDR5X
 
D3K said:
I'm surprised. I thought it was a given they were using HBM, with the only question being where they would source it from.

What does this mean for max memory on Ti's and Titans?
Click to expand...

I fully expect the big chips to come with HBM but looks like they are going with the pipe cleaners first and the bigger brothers will follow later. I was hoping vice-versa but hey ho.
 
Gregster said:
http://www.techspot.com/news/63436-nvidia-pascal-gp104-gpu-gddr5-hbm.html



Not surprised to read this and it was mentioned long ago that Nvidia would be using GDDR5X
Click to expand...

Good find, looks like the 970 / 980 replacements could be using GDDR5 then, HBM reserved for GP200? Disappointing imho, was hoping GDDR5 would be GTX 950 / 960 replacements only. Looks like the transition to HBM is going to be a slow one, imagine AMD will do the same thing.

Really hoping we don't have to wait until the end of the year for the real deal high end Nvidia cards..
 
Boomstick777 said:
Good find, looks like the 970 / 980 replacements could be using GDDR5 then, HBM reserved for GP200? Disappointing imho, was hoping GDDR5 would be GTX 950 / 960 replacements only. Looks like the transition to HBM is going to be a slow one, imagine AMD will do the same thing.

Really hoping we don't have to wait until the end of the year for the real deal high end Nvidia cards..
Click to expand...

These early news story's have been wrong in the past. We'll find out soon enough.
 
It seems HBM is still a PITA and still won't be available in quantity until way later in the year.

GDDR5X still allows double density over GDDR5 so you could have 24GB on a 384 bit bus. 32 on a 512.
 
Orangey said:
It seems HBM is still a PITA and still won't be available in quantity until way later in the year.

GDDR5X still allows double density over GDDR5 so you could have 24GB on a 384 bit bus. 32 on a 512.
Click to expand...

GDDR5x offers zero density improvement over gddr5. Gddr5 has been around for ages in 4Gb capacity but has been in production of 8Gb chips for some time, gddr5x is only 8Gb chips, it's just a dumb association that somehow gddr5 is 4Gb as standard because 8Gb chips haven't really made it into cards yet.

It will offer higher speeds, the key advantage really is higher speeds on a smaller bus. How much extra power is used with gddr5x at say 12Gbps vs gddr5 at 8Gbps, who knows. Theoretically you could have a 384bit bus using gddr5 8Gbps chips or 256bit bus and gddr5x 12Gbps chips and have the same bandwidth. 256bit bus would save die space, 384bit bus clocked lower might not use as much power.

Realistically if a high end 6-8TF/s chip needs 300+ Gb/s bandwidth today, a midrange gpu will need that in the next gen. Could mean midrange 350mm^2 Polaris having say a 384bit bus with gddr5x rather than needing a 512bit bus.

From what I've heard about HBM yields and interposer connecting yields and frankly Samsung/Hynix ability to produce memory I doubt the memory itself is any problem. Before Fury there was no effective production chain for attaching silicon chips to other silicon chips. We're talking a whole magnitude or two lower in scale when attaching TSV's as opposed to soldering bumps. You pretty much need foundry level clean room facilities to stick chips onto interposers. Producing chips is as easy to ramp up as any other chip before it. You have plants, you put in a different set of masks as they do today to switch between thousands of products being produced. Overnight you can turn down gddr5 production by 30% and replace it with HBM, that isn't even an issue. The issue is putting it all together on an interposer, that is almost certainly where the production bottleneck is and as with foundries, it won't be fixed overnight.

While you can switch gddr5 to hbm production literally overnight, you can't switch a current packaging facility over to interposer packaging overnight, you can't do it over a year, it's a multi year thing.

It won't take years from now, building will have started a long while back, but as with foundries you start something small and scale up.
 
I assume that a chip of this complexity would have to be designed for either HBM or GDDR being that the pin out needs are completely different, so surely that would mean that the memory type cannot be changed at the last minute, so these things have been planned this way for a long time.

Is there any chance that those shipping reports are just the GPU die's before being put on the interposers ?
 
bru said:
I assume that a chip of this complexity would have to be designed for either HBM or GDDR being that the pin out needs are completely different, so surely that would mean that the memory type cannot be changed at the last minute, so these things have been planned this way for a long time.

Is there any chance that those shipping reports are just the GPU die's before being put on the interposers ?
Click to expand...

With the modular nature of the GPU cores, it would be more of a matter of them designing the chips with a modular memory controller.

So for smaller chips the GPU will include the GDDR memory controller while the larger chips will include the HBM memory controller.

But yes, in terms of planning, it would have been something done ahead of time. Considering they have to produce the transfers for the lithography with the correct memory controller etc.
 
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bru said:
I assume that a chip of this complexity would have to be designed for either HBM or GDDR being that the pin out needs are completely different, so surely that would mean that the memory type cannot be changed at the last minute, so these things have been planned this way for a long time.

Is there any chance that those shipping reports are just the GPU die's before being put on the interposers ?
Click to expand...

37mm^2 is over twice the size of the biggest GPU Nvidia has ever made so... I'm going with nope ;)

Yes, they need different pinout, but also a different controller. Midrange will get made with a gddr5 controller, high end with hbm. I'm guessing there, might be low end gddr5, midrange/high end hbm.

Fury probably came as late as it did precisely because it was an HBM design. You gamble to a fair degree on new tech. They may have wanted that out a year earlier for all we know but you have to wait for HBM. AMD and Nvidia made designs for 20nm gpus, both gambled, both lost that one. AMD banked on what 65nm for the 2900xt, but the process was delayed and they had to push it back to 80nm which didn't work out great.

It's getting harder to make these choices work out as delays get longer as processes get more complex. Most gpus/cpus coming out say today are a result of decisions made 2-3 years ago at least. Zen really always had to be a 14-16nm design, if we had another year of 28nm Zen would get pushed way back. Intel has pushed two architectures back a year due to processes, broadwell out late and Kaby being inserted into the plan as 10nm pushed back has delayed plans for that architecture.

Memory controller is relatively easy to change, still it needs to be changed before the chip is finalised which would be pretty late on, probably a year out before full production, 6 months before tape out at a guess. The chip doesn't really care how the memory controller handles the data coming in and out as long as it can accept the same requests and provide the same data back. So all is that required is AMD make the memory controller that interfaces with the rest of the chip compatible which is pretty easy.
 
Mauller said:
With the modular nature of the GPU cores, it would be more of a matter of them designing the chips with a modular memory controller.

So for smaller chips the GPU will include the GDDR memory controller while the larger chips will include the HBM memory controller.

But yes, in terms of planning, it would have been something done ahead of time. Considering they have to produce the transfers for the lithography with the correct memory controller etc.
Click to expand...

Which would have been decided a long time ago, as it takes too long to make a change and then produce a new chip for this to be a recent decision.
 
bru said:
Which would have been decided a long time ago, as it takes too long to make a change and then produce a new chip for this to be a recent decision.
Click to expand...

yeah, unless it is an emergency refinement of a lithography pattern due to some design flaw, then they wouldn't have changed anything recently.
 
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