• Competitor rules

    Please remember that any mention of competitors, hinting at competitors or offering to provide details of competitors will result in an account suspension. The full rules can be found under the 'Terms and Rules' link in the bottom right corner of your screen. Just don't mention competitors in any way, shape or form and you'll be OK.

AMD demonstrates Ryzen 9 5900X prototype with 3D V-Cache stack chiplet design

Soldato
Joined
6 Feb 2019
Posts
10,248
Will this come to am4?

yes, the new CPU's are AM4 and compatible with all existing coolers, you dont have to change anything, you simply slot it into your motherboard

Also, anandtech has confirmed with AMD that the chiplet height remains the same, the CCX's have been machined down so the V-cache can sit on top without changing the CPU height - this maintains maximum compatibility.

But even more interesting, AMD told Anantech that they won't be stopping at just 1 V-cache layer, they can stack multiple layers, so potentialy they can make 16 core CPu's not just with 192mb L3 cache but even 384mb cache or maybe even 576mb L3 cache for Zen 4/Zen5

And what will be really fun with all this L3 cache is its big enough to install apps to it, we can have some fun by installing older games directly onto the CPU, or other apps
 
Soldato
Joined
30 Jun 2019
Posts
3,880
I doubt this will become a new generation of CPUs before Zen 4 is released next year, because they are still releasing Zen 3 CPUs (APUs) in August this year.

I think they will release 1 or 2 top high end products on socket AM4 (with high clocks), aimed at competing with Alder Lake CPUs in early 2022. Most Alder lake systems will still be using DDR4 RAM.

They will just but another X or T in the title, that seems to be how they market new CPUs of the same generation. There seems to be room for a '5900 XT' and '5950 XT' in the lineup.

I wonder if it would be worth fabbing them with TSMC's 6nm process?
 
Last edited:
Associate
Joined
11 Dec 2016
Posts
1,533
Location
Oxford
Can't see AMD releasing a new socket for zen 3 chips, so yes.
I don't understand. Zen3 chiplets give AMD the easiest route to AM5.
Glue Zen 3 chiplets to a DDR5 IO die and bam, you have a next generation platform. Then, to keep customers excited about it, glue a massive SRAM cache pool to chiplets (btw maybe AMD knows something we don't about DDR5 latency?).
That achieves parity with Alder Lake, both performance and release date. And buys some time to finish/polish 5nm production Zen 4.
 
Associate
Joined
31 Dec 2010
Posts
1,431
Location
Sussex
I doubt this will become a new generation of CPUs before Zen 4 is released next year, because they are still releasing Zen 3 CPUs (APUs) in August this year.

I think they will release 1 or 2 top high end products on socket AM4 (with high clocks), aimed at competing with Alder Lake CPUs in early 2022. Most Alder lake systems will still be using DDR4 RAM.

They will just but another X or T in the title, that seems to be how they market new CPUs of the same generation. There seems to be room for a '5900 XT' and '5950 XT' in the lineup.

I wonder if it would be worth fabbing them with TSMC's 6nm process?
Unless they have a need to release a pipe-cleaner to test out TSMC's 6nm I think that is unlikely.
TSMC's 6nm is said to use the same design rules as TSMC's 7nm but AFAIK that would still entail making a mask set etc. So not cheap or quick.
 
Associate
Joined
14 Nov 2005
Posts
1,258
I don't understand. Zen3 chiplets give AMD the easiest route to AM5.
Glue Zen 3 chiplets to a DDR5 IO die and bam, you have a next generation platform. Then, to keep customers excited about it, glue a massive SRAM cache pool to chiplets (btw maybe AMD knows something we don't about DDR5 latency?).
That achieves parity with Alder Lake, both performance and release date. And buys some time to finish/polish 5nm production Zen 4.
Why do you think AMD needs to achieve Parity with Alderlake. AMD are already ahead of Intel, the 3D stacking coming in Zen 3+ will give AMD an extra 15% on average which should be enough to keep the performance crown. If you are referring to parity in using DDR5 then i do not see that as a problem. Being first to the party is not always a good thing, early DDR5 will have little to no difference in performance to DDR4 so AMD have time on their side, wait a year till DDR5 is a little more worth while.
 
Associate
Joined
11 Dec 2016
Posts
1,533
Location
Oxford
Why do you think AMD needs to achieve Parity with Alderlake
AMD is ahead at this moment, but I expect Alder Lake is not a complete dud like 11th gen. There will be an IPC uplift, and Intel will be loud about it. DDR5, USB4 are nice buzzwords too. In any case, as Zen4 is currently projected end of 2022, AMD needs something earlier than that.
 
Associate
Joined
14 Nov 2005
Posts
1,258
AMD is ahead at this moment, but I expect Alder Lake is not a complete dud like 11th gen. There will be an IPC uplift, and Intel will be loud about it. DDR5, USB4 are nice buzzwords too. In any case, as Zen4 is currently projected end of 2022, AMD needs something earlier than that.
You must be expecting some massive gains from Alderlake if you think Intel will catch up on this Gen + the 15% of the new AMD variants. PCIE 4 came out with Zen 2 and it didnt really mean much to the average Joe buying a PC and still doesn't for that matter, Heck i do not even think it means that much to the enthusiasts at this moment in time either, in fact even in terms of NVME most of us would never notice the difference between PCIE 3 and 4 except for some extreme usage scenarios. So i doubt a buzz word will make much difference to be honest
 
Associate
Joined
31 Dec 2010
Posts
1,431
Location
Sussex
You must be expecting some massive gains from Alderlake if you think Intel will catch up on this Gen + the 15% of the new AMD variants. PCIE 4 came out with Zen 2 and it didnt really mean much to the average Joe buying a PC and still doesn't for that matter, Heck i do not even think it means that much to the enthusiasts at this moment in time either, in fact even in terms of NVME most of us would never notice the difference between PCIE 3 and 4 except for some extreme usage scenarios. So i doubt a buzz word will make much difference to be honest
For the well-informed, yes.
But if big numbers didn't impress people, marketing would keep trying them.
Even just sticking to storage, UDMA66/133 and SATA 1/2/3 were all marketed with headlines burst figures which seldom had any real-world benefit but unfortunately shifted lots of merchandise.
 
Associate
Joined
11 Dec 2016
Posts
1,533
Location
Oxford
You must be expecting some massive gains from Alderlake if you think Intel will catch up on this Gen + the 15% of the new AMD variants
Thats what I was saying. Unless AMD releases a +cache model, there is a danger Intel ends up on top until Zen 4.
Intel targets +20% IPC for Alder Lake. Meanwhile bigger cache +15% perf was shown only in select games (that are already known for liking large cache). For most benchmarks it won't be +15% IPC.

Zen3+ on AM5 makes sense for feature parity and to reduce pressure to release Zen4.
 
Caporegime
Joined
17 Mar 2012
Posts
40,392
Location
ARC-L1, Stanton System
Thats what I was saying. Unless AMD releases a +cache model, there is a danger Intel ends up on top until Zen 4.
Intel targets +20% IPC for Alder Lake. Meanwhile bigger cache +15% perf was shown only in select games (that are already known for liking large cache). For most benchmarks it won't be +15% IPC.

Zen3+ on AM5 makes sense for feature parity and to reduce pressure to release Zen4.
Intel said +20% for Rocket Lake over Comet Lake and everyone said to the critics of that: No no no.... this is a brand new architecture, Intel will crush AMD.

Intel need 20% just to catch Zen 3

bBRe00i.png
 
Associate
Joined
31 Dec 2010
Posts
1,431
Location
Sussex
Caporegime
Joined
17 Mar 2012
Posts
40,392
Location
ARC-L1, Stanton System
More digging around on the AT forums:
https://forums.anandtech.com/threads/speculation-zen-4-epyc-4-genoa-ryzen-6000.2571425/post-40514844
quoting this:

So basically saying the Zen3 CCDs already were designed for this from the beginning.
Possible just took longer to get to stacking: maybe the B2 revisions are something to do with getting this working?

From the Twitter string, There are TSV's all over the Zen 3 chip, yes Zen 3 was designed to be 3D stacked right from the start, and not just the Cache.

 
Associate
Joined
31 Dec 2010
Posts
1,431
Location
Sussex
From the Twitter string, There are TSV's all over the Zen 3 chip, yes Zen 3 was designed to be 3D stacked right from the start, and not just the Cache.

Things like release cycles, TSMC's and their packaging ability schedule all can slip.
So another big takeaway from this is great risk management from AMD since they could ship Zen 3 CCDs without that part being ready.
 
Caporegime
Joined
17 Mar 2012
Posts
40,392
Location
ARC-L1, Stanton System
Things like release cycles, TSMC's and their packaging ability schedule all can slip.
So another big takeaway from this is great risk management from AMD since they could ship Zen 3 CCDs without that part being ready.

AMD have a lot of wisdom when it comes to risk management, a decade of constantly being let down by GloFo.
 
Associate
Joined
11 Dec 2016
Posts
1,533
Location
Oxford
Top