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AMD demonstrates Ryzen 9 5900X prototype with 3D V-Cache stack chiplet design

This may explain the delays

https://www.reddit.com/r/hardware/comments/r0hj3r/my_expectations_for_ryzen_3d_vcache_performance/

Not only are 3D v cache chips harder to cool, but the extra cache modules steal power away from the cores, this means the cpu cores run roughly 10% lower clock speeds.

Now this makes AMDs benchmarks eye opening, because they compared 4ghz vs 4ghz which is well below non v-cache chip boost clocks and with this information it seems that new 3D v cache chips would have lower clocks all together.

The delays from AMD on launching the new CPUs may be them searching for further ways to tweak them for better power management. Perhaps they will just increase the TDP on all the models so they don't have to reduce clocks - but then you have extra heat to try and remove
 
Grim5 said:
This may explain the delays

https://www.reddit.com/r/hardware/comments/r0hj3r/my_expectations_for_ryzen_3d_vcache_performance/

Not only are 3D v cache chips harder to cool, but the extra cache modules steal power away from the cores, this means the cpu cores run roughly 10% lower clock speeds.

Now this makes AMDs benchmarks eye opening, because they compared 4ghz vs 4ghz which is well below non v-cache chip boost clocks and with this information it seems that new 3D v cache chips would have lower clocks all together.

The delays from AMD on launching the new CPUs may be them searching for further ways to tweak them for better power management. Perhaps they will just increase the TDP on all the models so they don't have to reduce clocks - but then you have extra heat to try and remove
Click to expand...

Cooling and power effects would have been obvious from the start.
 
Minstadave said:
Cooling and power effects would have been obvious from the start.
Click to expand...


Fair enough, it's something I never thought about till now.

AMD claimed games were running something like 15% faster with the extra cache at 4ghz. But when it comes to retail chips in the real world tests, it would likely be be under 15% because of the extra cache chips running lower clock speeds vs the lower cache chips.

What I find interesting is how AMD will choose to deal with that, on their server chips they've just lowered the base and boost clock speeds to retain the same TDP as the lower cache chips. And I'd be perfectly happy if AMD did the same thing with ryzen as it could potentially create more headroom for overclocking and that's more fun for us
 
Its taking power away from the cores due to the socket limitations, the TDP is for the CPU die only, the IO die uses another 20 to 25 watts making it about 130 watts, 10 watts away from the socket limit.

This would not mater in lighter workloads like games, as the package power is only around 50 to 70 Watts, so Zen 3D and Zen 3 will clock the same, in Cinebench and the like it might only run at 4Ghz vs 4.4Ghz, unless AMD figure a way round it....
 
Grim5 said:
This may explain the delays

https://www.reddit.com/r/hardware/comments/r0hj3r/my_expectations_for_ryzen_3d_vcache_performance/

Not only are 3D v cache chips harder to cool, but the extra cache modules steal power away from the cores, this means the cpu cores run roughly 10% lower clock speeds.

Now this makes AMDs benchmarks eye opening, because they compared 4ghz vs 4ghz which is well below non v-cache chip boost clocks and with this information it seems that new 3D v cache chips would have lower clocks all together.

The delays from AMD on launching the new CPUs may be them searching for further ways to tweak them for better power management. Perhaps they will just increase the TDP on all the models so they don't have to reduce clocks - but then you have extra heat to try and remove
Click to expand...

Uzzi who replied in the thread made a good point.

Milan-X has 4 SKUs. That means everything has to bin to those SKUs so expecting all the cores to clock the same as the fastest Milan SKUs seems a bit off considering there are several SKUs at the same core count level.
 
Grim5 said:
Not only are 3D v cache chips harder to cool, but the extra cache modules steal power away from the cores, this means the cpu cores run roughly 10% lower clock speeds.
Click to expand...

I think there's probably some truth in this. Adding some extra cache on top of the CPU die seems unlikely to grant extra performance for 'free'. I don't think there will be lower clockspeeds though (as it's the same Zen 3 architecture and very similar 7nm TSMC fabrication process), instead you will likely need a beefier cooler than with Zen3 CPUs, to cope with the higher power consumption. That could make these CPUs a more premium option than the Ryzen 5000 series.

Maybe the lower end models will be clocked a bit lower than the Ryzen 5000 series equivalents, to ensure these CPUs can be cooled affordably.

They probably used 4.0ghz in the performance slide to ensure a fair representation of any performance improvements.

One thing I'm sceptical about, is the amount of V-cache they will need to add to Zen 3 desktop CPUs. Do they really need more than double the total L3 cache of the Ryzen 5000 series? It's not cheap to produce.
 
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g67575 said:
I think there's probably some truth in this. Adding some extra cache on top of the CPU die seems unlikely to grant extra performance for 'free'. I don't think there will be lower clockspeeds though (as it's the same Zen 3 architecture and very similar 7nm TSMC fabrication process), instead you will likely need a beefier cooler than with Zen3 CPUs, to cope with the higher power consumption. That could make these CPUs a more premium option than the Ryzen 5000 series.
Click to expand...

This is how I hope AMD deals with driving more silicone. -Just allow the chips to more power.

I get the impression that the CCD's themselves are already tuned past the point of diminishing returns with respect to power, but the extra cash will need extra power, so just up the TDP and send it.
 
Distracted said:
Am I right in thinking that disabling cores will increase the per core cache availability for the remaining cores?
Click to expand...

Possibly, from what I’ve read, it seems like the additional cache is stacked directly on top of the existing L3 cache area and accessed through the same channel as the normal L3 cache too. So if disabled cores in existing CPUs increases per core cache availability, the same should hold for the stacked cache.
 
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