Caporegime
- Joined
- 18 Oct 2002
- Posts
- 33,188
That is a good point, I hadn't considered if it was physically possible for intel to compete on PCIE lanes. Is one of the reasons for this because AMD implementation of PCIE is more efficient than Intel?
More efficient, no not really, it's simply a case of die size more than anything else. AMD have a larger effective die by splitting it 4 ways and they can afford to go bigger because it's smaller dies. AMD literally couldn't make a chip with the same transistor count and same features if it was one die. GloFo has a current 600mm^2 reticule size, meaning it physically can't make chips with a die larger than that size, yet with 4 chips EPYC has something akin to a 770mm^2 of effective die size. Or another way to think of that, if AMD made a single monolithic die they'd have to cut out 170mm^2 of transistors and the things that would get cut to bring the size down would be a couple mem channels, a bunch of cores and a bunch of pci-e lanes.