Caporegime
Its not all about one man, Keller put together a capable team before he left, they will continue on that genius.
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*** AMD ThreadRipper ***
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Its not all about one man, Keller put together a capable team before he left, they will continue on that genius.
I didnt say it was but history isnt on the side of that suggestion, hopefully different this time!
Caporegime
With respect... Thats because you don't 'really know' what went on at AMD after Keller left.
It was a miss-judgement of where the market and technology was heading rather than AMD's execution of technology.
As far as AMD saw it the traditional X86 discrepancy between serial and parallel workloads was to become a thing of the past, applications would no long see it as one or the other but rather serial workloads would be instanced in parallel, A Heterogeneous System Architecture, The CPU would share its FP with the GPU, this was the purpose of Bulldozers modular design, they would simply be compute units, serial and parallel in the same package, 'APU's'.
AMD were wrong about where technology was heading, but the execution of the technology was genius, had it panned out for AMD things would be very different now.
An example of HSA working in traditional X86 floating point workloads.... and Jim Keller had nothing to do with any of this.
As you can see, the technology had a profound impact, it worked.
AMD are a very clever bunch without Keller.
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I have zero idea what this is supposed to mean, is abject market failure something deeper?With respect... Thats because you don't 'really know' what went on at AMD after Keller left.
It was a miss-judgement of where the market and technology was heading rather than AMD's execution of technology.
As far as AMD saw it the traditional X86 discrepancy between serial and parallel workloads was to become a thing of the past, applications would no long see it as one or the other but rather serial workloads would be instanced in parallel, A Heterogeneous System Architecture, The CPU would share its FP with the GPU, this was the purpose of Bulldozers modular design, they would simply be compute units, serial and parallel in the same package, 'APU's'.
AMD were wrong about where technology was heading, but the execution of the technology was genius, had it panned out for AMD things would be very different now.
An example of HSA working in traditional X86 floating point workloads.... and Jim Keller had nothing to do with any of this.
As you can see, the technology had a profound impact, it worked.
AMD are a very clever bunch without Keller.
Can you post the newest one?
Soldato
Just to check. Are 4 ram sticks required for threadripper? (Is it needed to correctly fill all the memory channels and get optimal bandwidth? I'm in the "2 big sticks" school of thought for regular desktop, I'm not after filling all available slots, I just don't want to miss easily available bandwidth.) Not messed with HEDT from either before, just pricing up.
Deleted member 66701
D
Deleted member 66701
Not required, but if you want the highest bandwidth, you want quad channel (4 or 8 sticks), but it will run in dual or single channel mode as well.
Soldato
Aye. I basically assumed it was quad channel DDR so 4 sticks would be the point where it uses all bandwidth but isn't being unduly hampered by having to drive too many sticks. Ty for confirming.
Caporegime
Threadripper is a 4 die EPYC CPU... there are 32 cores and 64 threads in them.
https://seekingalpha.com/article/41...c5d:815929faf6bebf7cde078bc1b54c4a88&uprof=55
https://seekingalpha.com/article/41...c5d:815929faf6bebf7cde078bc1b54c4a88&uprof=55
Threadripper is a 4 die EPYC CPU... there are 32 cores and 64 threads in them.
https://seekingalpha.com/article/41...c5d:815929faf6bebf7cde078bc1b54c4a88&uprof=55
Looks good for the future then. AMD must be in a pretty good place
Caporegime
24 core Threadripper incoming 
24 core Threadripper incoming
I really want a 48 thread system now!
Threadripper is a 4 die EPYC CPU... there are 32 cores and 64 threads in them.
https://seekingalpha.com/article/41...c5d:815929faf6bebf7cde078bc1b54c4a88&uprof=55
Not according to this article, threadripper and epyc are different, even down to the substrate.
https://www.overclock3d.net/news/cp..._on_the_threadripper_dummy_dies_controversy/1
That article basically says that right now there is no way to simply put in a live chip and hit a magic activate button. There is also not a way to magically add more ram channels so it is never going to reach Epyc performance on memory bandwidth. There is definitely a way they could add a second infinity fabric layer and put another two dies on the package, but the performance gains would be questionable and the development costs Vs volume of chips sold minimal.
I think that short term if you genuinely have a use case for more threads than threadripper you should probably be looking for the memory bandwidth and solution offered by the Epyc platform. If they follow the plan to die shrink to 7nm for Ryzen 2 then there is opportunity for them to ramp up speeds with the same number of cores and/or to add more cores to threadripper at that point. I believe on the current roadmap we are looking at 2018 or early 2019 for that which to be fair is probably when more of the industry will have caught up to the idea that these massive threadcounts are a real thing and develop pro-sumer software to work with them.
I think that short term if you genuinely have a use case for more threads than threadripper you should probably be looking for the memory bandwidth and solution offered by the Epyc platform. If they follow the plan to die shrink to 7nm for Ryzen 2 then there is opportunity for them to ramp up speeds with the same number of cores and/or to add more cores to threadripper at that point. I believe on the current roadmap we are looking at 2018 or early 2019 for that which to be fair is probably when more of the industry will have caught up to the idea that these massive threadcounts are a real thing and develop pro-sumer software to work with them.
Caporegime
AMD keep having to explain themselves, first saying Threadripper only had two dies, when der8auer took the lid off them to reveal 4 dies, AMD told him to remove all the imagery and said "oh two of them are dummy dies" now that der8auer actually took the dies apart to reveal real dies AMD are now saying "what we meant by dummy dies was actually real dies but not working" really?
Now they are saying they are not the same as EPYC, so why use a 4 dies package when you will only ever need two and why is the socket the same as EPYC? if you only ever intend to make a 2 die CPU them why make a more expensive 4 die CPU only to disable 2 of them? WTF?
Once again what AMD are saying doesn't add up.
The fact is they are EPYC CPU's with 2 dies disabled, you can't unblock them because they are disabled, if they don't disable them they are EPYC CPU's.....
To keep production cost down.
It might not be as simple as that. It's possible that they intended to make "dummy dies" (which would have to include some circuitry anyway, it's not like it can be a blank slab of silicon) but didn't have time or something and decided to just use disabled real dies, at least to start with. Or it might be that the cost to make the dies is so low that putting in disabled ones is cheaper over say a year than the cost to developing and productionising "dummy dies".
Caporegime
No, you're not fully addressing what i said, if AMD only ever intended to have a two die package CPU then why make a 4 die package?
AMD are trying to tell us its not EPYC, that's its different, so if its different then it has no use for the size of the thing and its very expensive 4096 pin TR4 socket, AMD are saying its a 2 die package.
So half the socket and its 4096 pins is useless, it has a figure of 8 Interposer... no one makes interposer's that shape.... if its intention was only ever to be a 2 die package then it would have been better and cheaper to design it as a 2 die package, not as a 4 die package apparently different to EPYC and then converted in a 2 die package with 2 dies added to it to hold up the far to big heat spreader. NO, of course not
Its an EPYC CPU that just didn't make the grade.
Caporegime
Does it really matter?
It does, it means there are 32 cores on Threadripper.
Soldato
No, you're not fully addressing what i said, if AMD only ever intended to have a two die package CPU then why make a 4 die package?
AMD are trying to tell us its not EPYC, that's its different, so if its different then it has no use for the size of the thing and its very expensive 4096 pin TR4 socket, AMD are saying its a 2 die package.
So half the socket and its 4096 pins is useless, it has a figure of 8 Interposer... no one makes interposer's that shape.... if its intention was only ever to be a 2 die package then it would have been better and cheaper to design it as a 2 die package, not as a 4 die package apparently different to EPYC and then converted in a 2 die package with 2 dies added to it to hold up the far to big heat spreader. NO, of course not
Its an EPYC CPU that just didn't make the grade.
TR was a late design choice. We knew there would be what is now the Ryzen line, and there had to be a Opteron follow up. No one was predicting a HEDT platform above 8C16T from AMD. TR is Epyc because the yields are crazy good and possibly a way to dispose of dies with issues in IF or packaging problems. IMO, of course