Caporegime
-
Competitor rules
Please remember that any mention of competitors, hinting at competitors or offering to provide details of competitors will result in an account suspension. The full rules can be found under the 'Terms and Rules' link in the bottom right corner of your screen. Just don't mention competitors in any way, shape or form and you'll be OK.
*** AMD ThreadRipper ***
- Thread starter Boomstick777
- Start date
Ive always read that stuff from AMD to mean its Epyc packaging around 2 functioning threadripper die's and two faulty threadripper die's which are disabled)
From AMD's point of view why NOT make TR and Epyc with the same packaging - makes a lot of sense production wise and makes both chips slightly cheaper
(well to be fair it should make Epyc slightly cheaper and TR a lot cheaper - because otherwise they would have to use a totally different package for TR with all the costs of designing implementing that)
This doesn't make much sense to me - but seems to be the approach AMD are taking. Aside from failed substrate/interposer TR and Epyc should be binned chips with fairly low failure rates on the constructed CPU. Its possible that TR might be a mix of failed Epyc packages that have 2 chips working and some made intentionally as TR which might be why they are all built around 4 chips for simplicity.
Caporegime
I read AMD's responses to this as a bit misleading to be honest, its like they are trying to say its a different CPU all together, in fact that is what they did say.
I don't know why they can't just say they are salvaged EPYC's, thats what they are.
I don't know why they can't just say they are salvaged EPYC's, thats what they are.
Soldato
Aside from IBM no one has really been pushing MCM. No idea the failure rate but it's logical to assume there is some redundancy in IF if the interconnect to a chip is "iffy". It's also possible that die with bad IMC can be used to populate the TR package to make IF work. Fact is we probably won't know until ten years time when someone does a write up on the Zen years
Also, "Buy our amazing product X, it's salvaged from the more expensive product Y!" said no marketing department ever
Caporegime
Good point.
Aside from IBM no one has really been pushing MCM. No idea the failure rate but it's logical to assume there is some redundancy in IF if the interconnect to a chip is "iffy". It's also possible that die with bad IMC can be used to populate the TR package to make IF work. Fact is we probably won't know until ten years time when someone does a write up on the Zen years
Also, "Buy our amazing product X, it's salvaged from the more expensive product Y!" said no marketing department ever
Would make sense to have some redundancy in the interconnect to offset failure but no idea if AMD do that. MCM isn't that unusual though - as mentioned before Intel slapped multiple dies on some of their CPUs back in the late P4/Core 2 days and AMD did it with some Opterons, etc.
Product association if done correctly is quite powerful in marketing though - obviously slapping salvaged all over it probably wouldn't give the right impression but association with a more expensive product tends to work quite a lot subconsciously on consumers
No it doesn't
Just because someone on YT has said there complete don't mean they worked but have been disabled.
It's more than likely to be naff dies thus why AMD calls them dummy dies.
Caporegime
I'm not sure AMD do love to sell more than what's advertised.
It's simple, 2 dies are top 5% bin like AMD themselves said and the other 2 are failed dies, unrecoverable due to various defects and would be destined for the landfill otherwise.
I presume AMD wanted to be vague there because yields are a closely guarded secret and this might give Intel some hints.
I presume AMD wanted to be vague there because yields are a closely guarded secret and this might give Intel some hints.
Aside from IBM no one has really been pushing MCM. No idea the failure rate but it's logical to assume there is some redundancy in IF if the interconnect to a chip is "iffy". It's also possible that die with bad IMC can be used to populate the TR package to make IF work. Fact is we probably won't know until ten years time when someone does a write up on the Zen years
Also, "Buy our amazing product X, it's salvaged from the more expensive product Y!" said no marketing department ever
It's no coincidence that threadripper/epyc is as it is and the IBM connection is of course there seen as GlobalFoundries acquired IBM's micro electronics division back in 2015. The acquisition included a significant amount of IP which you would have to say helped guide a path for AMD's Ryzen, when your designing for effectively an ibm process you make the most of its strong points. I find the whole thing really interesting and work for the company that facilitated the transfer of that IP.
Soldato
Far as I can see, to go beyond the 16 core 32 thread limit on threadripper would require another die to be active which means another pair of memory channels and the extra pci-e lanes that each die has.
Soldato
Assuming IF can't be configured to just route existing memory and PCIe lanes to extra x86 compute units. The whole idea of network on chip is to be able to drop in feature blocks as and when needed. There is no reason (aside from cost and demand) why AMD couldn't drop an ASIC, some GPU compute units and some memory in there too
Soldato
Well since there is talk of going from 4 core to 6 core for AMD anyways then we will be going from 16 core threadripper to 24 core on their next version anyways.
But yes they are likely dead yield and they are not disabled, but they are not even connected to anything because the controller doesn't have amything to make them possible then I would say it is redundant to sugget we can have a 32 core threadripper.
Humbug, we had the information stating they are using the Epyc stuff because it didn't cost them development or similar for another socket and also because it wouldn't fit in a Ryzen socket. That seems logical since they were never going to exist.
With that it does of course mean in future iteration then we could have 48 core 96 threads threadripper in future generations if AMD wished.
But yes they are likely dead yield and they are not disabled, but they are not even connected to anything because the controller doesn't have amything to make them possible then I would say it is redundant to sugget we can have a 32 core threadripper.
Humbug, we had the information stating they are using the Epyc stuff because it didn't cost them development or similar for another socket and also because it wouldn't fit in a Ryzen socket. That seems logical since they were never going to exist.
With that it does of course mean in future iteration then we could have 48 core 96 threads threadripper in future generations if AMD wished.
Last edited:
Caporegime
Nice, is that 24/7 stable? ^^^^