AMD VEGA confirmed for 2017 H1

[Rroff]

established member or not, everyone has the right to speak their mind. people will call out any rude / stupid remarks whoever they might come from

Problem is when you get people hiding behind a new alt account to say things they wouldn't on their normal one like calling people out.

 

[r7slayer]

especially in fanboy threads like these.

AMD VEGA confirmed for 2017 H1 is a fanboy thread? Ohh jeeze man no wonder i never see any news then

 

[Rilot]

Apologies all, did not realise i needed to be a long term member before i could make an observation wont happen again.

You do not, and anyone saying so is out of line.

 

[nashathedog]

AMD VEGA confirmed for 2017 H1 is a fanboy thread? Ohh jeeze man no wonder i never see any news then

I think he means what it's turned in to rather than it's original intended use. Pretty much every "We will have to wait for more info" thread turns in to a tit for tat brand war between opposing members. Sad really.

PS, Tongue in cheek, I know

 

[r7slayer]

I think he means what it's turned in to rather than it's original intended use. Pretty much every "We will have to wait for more info" thread turns in to a tit for tat brand war between opposing members. Sad really.

Yea i guess this is true unfortunately. I guess its the wait which turns members into bickering about odd bit of news lol. Ill admit being pulled into it at times but generally i do come in look and hoping to see some news before going on google and looking my self.

 

[Deathroned]

especially in fanboy threads like these.

As per usual i will reserve judgment for when i have one in my hands.

I don't believe AMD's marketing slides anymore than i believe Nvidias....

of course, you get to play with the wares, whilst we salivate, tell us how is Zen I know 8pack, Gibbo, Roman and possibly Bicepo are excited.

 

[JediFragger]

You do not, and anyone saying so is out of line.

It was the 'you'll be embarrassed when wrong' stuff that rubbed me, he was obviously posting some info and speculating on its outcome.

Hey ho, different horses for different courses...

 

[melmac]

Apologies all, did not realise i needed to be a long term member before i could make an observation wont happen again.

your comment was fine, not only was it fine, it was totally accurate.

Problem is when you get people hiding behind a new alt account to say things they wouldn't on their normal one like calling people out.

Except in this case who would bother creating a new account to call AthlonXP1800 out? Everybody here knows that he only posts anti-AMD BS, most people just ignore it.

 

[Legend]

Problem is when you get people hiding behind a new alt account to say things they wouldn't on their normal one like calling people out.

People do that? That's ridiculous. On a separate note, that Legend guy who posts here is a real smart guy, always says interesting stuff. Oh, hang on, who am I logged in as... OH NO!

Anyway, I wonder if we'll get a reliably firm release date for VEGA announced at CES? So many unknowns from AMD at the moment what with Ryzen hovering as well. I just hope they don't dilly dally, but at the same time don't rush a half baked product just to try and steal thunder from Intel and Nvidia.

 

[Rroff]

People do that? That's ridiculous. On a separate note, that Legend guy who posts here is a real smart guy, always says interesting stuff. Oh, hang on, who am I logged in as... OH NO!

Anyway, I wonder if we'll get a reliably firm release date for VEGA announced at CES? So many unknowns from AMD at the moment what with Ryzen hovering as well. I just hope they don't dilly dally, but at the same time don't rush a half baked product just to try and steal thunder from Intel and Nvidia.

It happens - not saying it is the case here.

 

[N19h7m4r3]

Apparently someone has been going through AMD's patents for Vega and made this post on reddit. Pinch of salt folks, but a nice little post.



https://www.reddit.com/r/Amd/comments/5lqale/vega_vs_gcn_architecture_in_pictures/

I was discussing this NCU design in the other thread. AMD is going to a new variable width SIMDs, and a beefed up Hardware Scheduler that will be able to best fit the workload to each SIMD to fully utilize it.
The really good thing about the variable design is the different ratio SIMDs can combine to process an instruction or shader that requires 16-wide ALUs, so there is no situation in which this design is worse than the current 4x SIMD of 16 ALUs. But for gaming, there will be a huge efficiency win.

I've read a few of their patents awhile back, AFAIK, this isn't a tile based rasterizer, but simply a more efficient rasterizer in general.
Though contrary to the myth that AMD's rasterizer is what's holding them back, it's actually not true. ROP bottleneck will show a distinct behaviour in games, as resolution rises, the relative performance will drop. Anyone who has paid attention with GCN knows that as resolution goes up, it's relative performance is actually stronger.
AMD's biggest problem with GCN is the inability of most game engines fully utilizing it's shaders. We've seen what can happen with good programmers with Doom Vulkan, using Shader Intrinsics and Async Compute to max out GCN, RX 480 ~20% faster than 1060, which actually matches it's paper TFlops specs. In most games for GCN, there's a lot of SIMDs with idling ALUs doing nothing so in effect, it's not a 5.8 TFlop GPU since that rating is the max theoretical perf assuming all ALUs are working.
Going with NCU's variable width SIMD layout will solve this issue, so we should get a more closer and truer comparison of paper spec TFlops to gaming performance. ie. A Vega of 12.5 TFlops will absolutely wreck Fury X.
Btw, per the patents, it's not all variable width SIMDs. Each CU has 1x 16 wide SIMD, and 3 to 5 (depending on the configuration) of variable width SIMDs (12,8,6,4) along with twice the Scalar ALUs (that are extremely fast at processing some shader instructions, think of it as a "bypass traffic, go super speed") of current GCN per CU.
All of this sounds great, the obvious question would be, why didn't AMD go with this design from the start? Why the 4x 16 width SIMD layout that they would have known would have issues with under-utilization? It's all down to the feedback mechanisms and a really dynamic hardware scheduler required, to be able to combine multiple variable SIMDs to process instructions that require 16-ALU SIMDs. AMD just didn't have this tech back then as we see their patents, the bulk of it addresses this new HWS technology to enable this kind of design.

 

[Griffildur]

+1

...and we have all made a few of those in our time here. LOL

I have absolutely no idea what you are talking about ... none ...

 

[humbug]

Apparently someone has been going through AMD's patents for Vega and made this post on reddit. Pinch of salt folks, but a nice little post.



https://www.reddit.com/r/Amd/comments/5lqale/vega_vs_gcn_architecture_in_pictures/

I've read a few of their patents awhile back, AFAIK, this isn't a tile based rasterizer, but simply a more efficient rasterizer in general.
Though contrary to the myth that AMD's rasterizer is what's holding them back, it's actually not true. ROP bottleneck will show a distinct behaviour in games, as resolution rises, the relative performance will drop. Anyone who has paid attention with GCN knows that as resolution goes up, it's relative performance is actually stronger.
AMD's biggest problem with GCN is the inability of most game engines fully utilizing it's shaders. We've seen what can happen with good programmers with Doom Vulkan, using Shader Intrinsics and Async Compute to max out GCN, RX 480 ~20% faster than 1060, which actually matches it's paper TFlops specs. In most games for GCN, there's a lot of SIMDs with idling ALUs doing nothing so in effect, it's not a 5.8 TFlop GPU since that rating is the max theoretical perf assuming all ALUs are working.
Going with NCU's variable width SIMD layout will solve this issue, so we should get a more closer and truer comparison of paper spec TFlops to gaming performance. ie. A Vega of 12.5 TFlops will absolutely wreck Fury X.
Btw, per the patents, it's not all variable width SIMDs. Each CU has 1x 16 wide SIMD, and 3 to 5 (depending on the configuration) of variable width SIMDs (12,8,6,4) along with twice the Scalar ALUs (that are extremely fast at processing some shader instructions, think of it as a "bypass traffic, go super speed") of current GCN per CU.
All of this sounds great, the obvious question would be, why didn't AMD go with this design from the start? Why the 4x 16 width SIMD layout that they would have known would have issues with under-utilization? It's all down to the feedback mechanisms and a really dynamic hardware scheduler required, to be able to combine multiple variable SIMDs to process instructions that require 16-ALU SIMDs. AMD just didn't have this tech back then as we see their patents, the bulk of it addresses this new HWS technology to enable this kind of design.

This is significant.
For at least a couple generations now Nvidia have been able to do more with less than AMD through technologies like this, its technologies like this that Nvidia have also been claiming as their own, no doubt to keep that competitive edge.
All that was turned on its head when Nvidia challenged Samsung and Qualcomm in court with claims of stealing IP in their use of technology like this for their mobile SOC's, Nvidia lost and the precedent was set that Nvidia do not own the IP for said technologies, paving the way for AMD to use them too.

It looks like Vega are those GPU's.

For about 3 generations AMD have had to make bigger brute-force GPU's more compact and more efficient to keep up, with all AMD learned from that and now able to use these technologies it should be pretty interesting looking ahead from here.

Spoiler

Thank you Samsung

 

[D1craig]

It was the 'you'll be embarrassed when wrong' stuff that rubbed me, he was obviously posting some info and speculating on its outcome.

I think perhaps we may know more from CES, would be embarrassed for you if your information turns out not to be the fact your post is claiming it to be.

Maybe if you read the post correctly it would not have rubbed you so wrongly?

 

[Rroff]

This is significant.
For at least a couple generations now Nvidia have been able to do more with less than AMD through technologies like this, its technologies like this that Nvidia have also been claiming as their own, no doubt to keep that competitive edge.
All that was turned on its head when Nvidia challenged Samsung and Qualcomm in court with claims of stealing IP in their use of technology like this for their mobile SOC's, Nvidia lost and the precedent was set that Nvidia do not own the IP for said technologies, paving the way for AMD to use them too.

It looks like Vega are those GPU's.

For about 3 generations AMD have had to make bigger brute-force GPU's more compact and more efficient to keep up, with all AMD learned from that and now able to use these technologies it should be pretty interesting looking ahead from here.

Spoiler

Thank you Samsung

I think one thing people seem to be missing is that AMD is moving away from discrete blocks for some fundamental functionality - which has traditionally meant that throughout the AMD lineup GPUs that are based off the same core are only separated for performance in those areas by clock speed and unlike nVidia where that has been moved to the shaders for awhile they don't scale up with larger implementations of the core - while it is only a relatively small part of what makes up the overall performance of the GPU it should help AMD to be move competitive at the top end of their lineup (in a similar way to the tiled/binned rasterisation would scale with bigger GPUs).

 

[Orcvader]

Apparently someone has been going through AMD's patents for Vega and made this post on reddit. Pinch of salt folks, but a nice little post.

http://i.imgur.com/ZHoEgS0.jpg?1

https://www.reddit.com/r/Amd/comments/5lqale/vega_vs_gcn_architecture_in_pictures/

Noticed this as well, if true then Vega should have no issues performing at full utilization as well as being a lot more power efficient. Should also mean each unit won't need as much die space compared to GCN, so assuming the overall die size is around full Pascal size, it should be a very competitive chip. Maybe the hints of Vega actually going against Volta is true after all...

Hopefully Thursday's presentation should clear things up.

 

[Mauller]

Further info picked up from a recent AMD patent. If what this patent is talking about is 'Draw Stream Binning Rasteriser' related then it points to it being a Tiled based Rasteriser.

http://www.freshpatents.com/-dt20161222ptan20160371873.php

Quote
'A primitive batch is generated from a sequential sequence of primitives.
A first bin intercept is identified for primitives as they arrive in
the primitive batch. After a batch is closed, a first bin for processing
is identified. The bin corresponds to a region of a screen space.
Primitives intercepting the identified bin are processed. For each
primitive intercepting the identified bin, a next bin intercept is
identified and the pixels included in the primitive that are enclosed by
the identified bin are sent for detailed rasterization. . The process
is repeated for any bins intersected by a primitive of the primitive
batch.'

 

[humbug]

I think one thing people seem to be missing is that AMD is moving away from discrete blocks for some fundamental functionality - which has traditionally meant that throughout the AMD lineup GPUs that are based off the same core are only separated for performance in those areas by clock speed and unlike nVidia where that has been moved to the shaders for awhile they don't scale up with larger implementations of the core - while it is only a relatively small part of what makes up the overall performance of the GPU it should help AMD to be move competitive at the top end of their lineup (in a similar way to the tiled/binned rasterisation would scale with bigger GPUs).

AMD's original GCN designs probably seemed like a good idea at the time trying to get into Workstations but no they don't scale, Cite Fury-X, a huge and hugely powerful GPU in terms of raw throughput, but strangled to death, literally.

TBH i thought some of AMD's problems stem from not having tiled resources, shading / rasterization, i still do but apparently not, i think now perhaps not so much but it would still help.

In any case which ever way round its achieved using resources more intelligently is the only way forward.

 

[flopper]

This is significant.
For at least a couple generations now Nvidia have been able to do more with less than AMD through technologies like this, its technologies like this that Nvidia have also been claiming as their own, no doubt to keep that competitive edge.
All that was turned on its head when Nvidia challenged Samsung and Qualcomm in court with claims of stealing IP in their use of technology like this for their mobile SOC's, Nvidia lost and the precedent was set that Nvidia do not own the IP for said technologies, paving the way for AMD to use them too.

It looks like Vega are those GPU's.

For about 3 generations AMD have had to make bigger brute-force GPU's more compact and more efficient to keep up, with all AMD learned from that and now able to use these technologies it should be pretty interesting looking ahead from here.

Spoiler

Thank you Samsung

Anew Era awaits that is brightening the horizon as Zenengineers worked on the Vega technology to adjust the conformity towards mobility and flexibility.
Releasing the power to make some noise as the drums in the deep starts your awaken

 

[N19h7m4r3]

Noticed this as well, if true then Vega should have no issues performing at full utilization as well as being a lot more power efficient. Should also mean each unit won't need as much die space compared to GCN, so assuming the overall die size is around full Pascal size, it should be a very competitive chip. Maybe the hints of Vega actually going against Volta is true after all...

Hopefully Thursday's presentation should clear things up.

While I still think the "volta/voltage" part of that video refers to their own Power usage issues, I do hope Vega is not just another GCN iteration.

I do like GCN, and it does have a lot of longevity, but they need to get away from it to get performance per watt back, while making larger jumps in over all performance.

Who knows if these patents are implemented in Vega, or if it's not for Navi; I just hope Vega does give AMD the performance jump they so desperately need.

Hopefully the upcoming event is better than the previous show casings; where with even Polaris they barely revealed anything until it actually launched.