My point was TSMC were able to produce a L1 cache design that operated above 5GHz using their 7nm process, which as Beren points out, was quite early on in its development. This is significant for 2 reason:
1: L1 cache frequency determines CPU max frequency, so if a L1 cache design can operate at 5GHz then the CPU as a whole will not be hampered by cache frequency limits
2: TSMC demonstrated their manufacturing process is capable of reaching those frequencies, so the node itself would not be a performance bottleneck, as was the case with GloFo's 14nm and 12nm.
So what I was saying is that the Zen 2 architecture operating at 5GHz is not an impossibility; both the cache design and the process node are capable of doing so.