x86 is RISC internally. It's just the instruction set that's CISC, but it gets broken down into RISC in the frontend stage.
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AMD Zen 5 rumours
- Thread starter Grim5
- Start date
Again no, the AGESA SoC voltage was left unlocked, like core voltages and IMC voltages.... for overclocking, right to the point of extreme overclocking, which is a thing.
Asus just didn't read AMD's white paper for voltage guidelines, or they ignored it to chase higher memory stability at the higher XPO clocks.
AMD later locked the SoC voltages to 1.3v in the AGESA because if you can't play nice with your toys we will take them away.
We need to stop blaming CPU vendors for mistakes made by motherboard vendors, its their responsibility to set the out of box voltages from those guidelines, if board vendors making the motherboard set the wrong out of box voltages that is nothing to do with AMD, that's the board vendors responsibility.
A bit of commons sense on our part, because for the sake of being an Asus fanboi we are being self destructive, both for Intel and AMD leaving all these voltages unlocked so we can play with them being enthusiasts comes from being high trust on Intel's and AMD's part, if we are going to start blaming them for that high trust when idiots get it wrong then they will think again about that trust and take our toys away.
Stop it.
PS: you can run 1.55v SoC under LM2 no problem, but not under conventional cooling! In the same way you wouldn't run your CPU at 1.7v under conventional cooling.
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AMD shares some responsibility for the SOC voltage issues, if you release a chip unlocked you must take the hit when things go bang. AMD new what board venders would release before end user got them. Only a very small number of chips got damaged before they locked it down which make me think that the actual safe SOC voltage for OC RAM was not fully known as 99.99% might be fine at high SOC values. At the end of the day, the release spec and what hits retail is always very different which is why boards should have LN2 physical switches to prevent accidental damage. Just saying, they left it unlocked for LN2 is not acceptable as only a very small number of users would ever do that.
Not blaming the CPU vendor, but the released firmware update fixed the issues.
There was reports that gigabyte was having voltage issues aswell,
And I'm sure I read that asrock also had an issue with a failed CPU.
Asus do deserve blame for pushing the voltages, but at the same time if an agesa update was required to permanently fix the issues then it can't be just a motherboard vendor issue, especially as all motherboard vendors had to issue bios updates as soon as the new agesa update was launched.
Although I've got an Asus board I'm not an Asus fan boy they just so happened to have a quality enough board with the features I wanted at the price I wanted to pay. I actually wanted an gigabyte board, me and my brother usually tend to stick to gigabyte over the past 20 year (Christ I feel old thinking about it) but there was no stock anywhere at the time.
@FredFlint @sx_turbo
The SoC voltage for Ryzen has been know for years, its 1v to 1.1v stock and 1.1v to 1.25v for EXPO, you would be daft to run it anything over 1.3v, we know this because AMD have said this so many time in many different ways.
Along comes Asus and throws that knowledge in the bin and has the SoC running at anything up to 1.6v (utterly ridiculous, i mean are you actively trying to kill it?????) for EXPO and its AMD's fault? AMD do not set those voltages, in the same way they do not reach in to your motherboard and set your voltages, you're doing that and if you didn't then who ever made your motherboard did.
If i'm chasing 4000MT/s RAM and keep upping the voltage until i reach that stable but end up at 1.56v, and my CPU goes *pop* 6 weeks later whose fault is that? is that AMD's fault for allowing me to do that? Because that is what we are saying here.....
The SoC voltage for Ryzen has been know for years, its 1v to 1.1v stock and 1.1v to 1.25v for EXPO, you would be daft to run it anything over 1.3v, we know this because AMD have said this so many time in many different ways.
Along comes Asus and throws that knowledge in the bin and has the SoC running at anything up to 1.6v (utterly ridiculous, i mean are you actively trying to kill it?????) for EXPO and its AMD's fault? AMD do not set those voltages, in the same way they do not reach in to your motherboard and set your voltages, you're doing that and if you didn't then who ever made your motherboard did.
If i'm chasing 4000MT/s RAM and keep upping the voltage until i reach that stable but end up at 1.56v, and my CPU goes *pop* 6 weeks later whose fault is that? is that AMD's fault for allowing me to do that? Because that is what we are saying here.....
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Expecting board venders and users to not exceed the spec even though they always do is stupid, more so for RAM OC’s considering they ALL advertise it. Hardware has safeguards built in for a reason, you can NEVER trust third party input. Allowing unreasonable input voltages is dangerous, all hardware venders know this and have safeguards in place. Also, The IO die for 7x chips is very different to previous generations so comparing voltage limits is not useful as it’s a new node, memory type and has an iGPU. I have not seen anyone quoting > 1.6v as the value been used, from what I have read most chips failed at 1.30-1.45v. ASUS was said to be upto +0.08v but it depends where the prob is positioned for testing. Some boards survived as the safeguards kicked in (as they should) others did not and that is down to the vender, but the CPU should also protect itself.
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No.... IMO this sort of normelisation of what is regrertion, something worse, is not healthy.
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Same here if performance isn't compromised and efficiency is improved. The less power they draw overall is a massive consideration and when browsing or doing basic things why bother using the power cores. As you say though it needs correct implementation.
"its good because power efficiency" AMD with its all big core designs are more power efficient in every device you find them in.
Intel did it because their designs don't allow them to keep up with AMD in Cinebench MT with an all big core CPU, that's it, to detract from that they borrow some ARM marketing.
Its an 8 core CPU with a couple of older gen i5 CPU's glued to the side, if you ever come across a game that uses more than 8 cores to feed the GPU now or in the future you will know how true that is, its a "Compromise CPU"
Intel did it because their designs don't allow them to keep up with AMD in Cinebench MT with an all big core CPU, that's it, to detract from that they borrow some ARM marketing.
Its an 8 core CPU with a couple of older gen i5 CPU's glued to the side, if you ever come across a game that uses more than 8 cores to feed the GPU now or in the future you will know how true that is, its a "Compromise CPU"
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You guys do know AMD's c cores are not "little cores" Right? They are identical to the big cores, they have the same IPC, they are simply more tightly packaged. Its not about power, its about packaging, space.
Its how they get a 128 core CPU in the same space as a 96 core CPU. The difference in that packaging means they don't clock as high. which for hyperscaling servers is irrelevant. Its a more specific product for a specific use case.
Its how they get a 128 core CPU in the same space as a 96 core CPU. The difference in that packaging means they don't clock as high. which for hyperscaling servers is irrelevant. Its a more specific product for a specific use case.
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Not really only thightly packaged, zen5 c has less cache per core.
It isn't just because of less cache per core though - they are more tightly packed as they use denser design libraries (in layman's terms as the frequency targets aren't as high things can be closer together without interference becoming a problem), and have the TSVs used for 3D stacking removed
The end result is an overall size reduction 2.48mm2 for zen4c vs 3.84mm2 for standard zen4 cores
Zen 4 - Wikipedia
It isn't just because of less cache per core though - they are more tightly packed as they use denser design libraries (in layman's terms as the frequency targets aren't as high things can be closer together without interference becoming a problem), and have the TSVs used for 3D stacking removed
The end result is an overall size reduction 2.48mm2 for zen4c vs 3.84mm2 for standard zen4 cores
Zen 4 - Wikipedia
en.wikipedia.org
So in effect they are actually efficiency cores, but designed a different way ? Less voltage required, lower top frequency ?
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