Intel Core Ultra 9 285k 'Arrow Lake' Discussion/News ("15th gen") on LGA-1851

[jigger]

You can keep repeating that as often as you like, but it doesn't make it true.

Golden Cove had significant improvements:

Popping the Hood on Golden Cove

Alder Lake (ADL) is the most exciting Intel launch in more than half a decade.

chipsandcheese.com

Oh yeah look, a wider more parallel version of something that looks rather similar to the Skylake design. You can keep arguing it’s not the case, but that’s been the Intel strategy.

 

[Armageus]

Oh yeah look, a wider more parallel version of something that looks rather similar to the Skylake design.

May as well call it Haswell then, because Skylake was just a slightly wider more parallel version of something that looks like Haswell.
(Which in turn was a Wider version of Ivy Bridge)

Skylake: Intel’s Longest Serving Architecture

Intel debuted Skylake in 2015.

chipsandcheese.com

You can keep arguing it’s not the case, but that’s been the Intel strategy.

And why is identifying bottlenecks in an existing architecture and fixing them in improved versions such an issue for you?

Why don't AMD get the same criticism from you? After all Zen 4 is just a wider version of Zen 3, itself a wider version of Zen 2, itself just a manufacturing/packaging change compared to Zen+/Zen



Don't get me wrong, I absolutely get the hate for Kaby Lake/Coffee Lake/Comet Lake which was essentially just rebranding of Skylake, but you can't continue to apply that ad-infinitum to everything since

 

[jigger]

May as well call it Haswell then, because Skylake was just a slightly wider more parallel version of something that looks like Haswell.
(Which in turn was a Wider version of Ivy Bridge)

Skylake: Intel’s Longest Serving Architecture

Intel debuted Skylake in 2015.

chipsandcheese.com

And why is identifying bottlenecks in an existing architecture and fixing them in improved versions such an issue for you?

Why don't AMD get the same criticism from you? After all Zen 4 is just a wider version of Zen 3, itself a wider version of Zen 2, itself just a manufacturing/packing change compared to Zen+/Zen

Just calling it as it is. I have called the P core version .X ringbus+Atom in the past.

Intel had its tick tock strategy and dropped the tick. Now the strategy is tock plus E cores and accelerators, but ultimately the goal will be a ground up new architecture with scalability.

Also, Intels current desktop design isn’t an issue for me at all. Intel have to work with the hardware they have and the situation is what it is.

Rroff and I were discussing the merits and drawbacks of Intel dropping HT from its desktop parts. Intel will be killing HT for a reason.

 

[humbug]

May as well call it Haswell then, because Skylake was just a slightly wider more parallel version of something that looks like Haswell.
(Which in turn was a Wider version of Ivy Bridge)

Skylake: Intel’s Longest Serving Architecture

Intel debuted Skylake in 2015.

chipsandcheese.com

And why is identifying bottlenecks in an existing architecture and fixing them in improved versions such an issue for you?

Why don't AMD get the same criticism from you? After all Zen 4 is just a wider version of Zen 3, itself a wider version of Zen 2, itself just a manufacturing/packaging change compared to Zen+/Zen



Don't get me wrong, I absolutely get the hate for Kaby Lake/Coffee Lake/Comet Lake which was essentially just rebranding of Skylake, but you can't continue to apply that ad-infinitum to everything since

He's right, Zen 2 is a significant enhancement of Zen 1, Zen 3 a significant enhancement of Zen 2, Zen 4 a significant enhancement of Zen 3 and it looks like Zen 5 is a significant enhancement of Zen 4.

Zen 1 was a different architecture to Excavator which was a significant enhancement of Piledriver which was a rebranded slightly improved Bulldozer.

Golden Cove is a different architecture to Skylake. However 12'th gen, 13'th gen and 14'th are nothing more than rebranded slight improvements on Golden Cove, 12'th gen, Arrow Lake, 15'th Gen looks like its a significant enhancement on Golden Coved.

AMD do put more work in to each new CPU they release while still keeping long term socket compatibility, amazing... while Intel use the 'Add more cores' Strategy, Ironic.... But Golden Cove is not Skylake. Had you said Raptor Lake is the same as Golden Cove i would have agreed, it is...

PS: i hate Intel's core naming scheme, its hard to keep up with it, the numbers game, Zen 1, 2, 3, 4, 5. Is nice and easy to keep up with.

 

[malachi]

I'm surprised HT has been around for this long. I thought its days would be numbered soon as multi-core became the norm.​

 

[Rroff]

I'm surprised HT has been around for this long. I thought its days would be numbered soon as multi-core became the norm.​

HT has a lot of benefits beyond just raw performance. Ignoring the advent of E cores for a moment even in situations where HT can't contribute to increasing performance on a task if you have all physical cores loaded up on a task system responsiveness can suffer, enable HT and you lose maybe 5% performance on that task but system responsiveness is still maintained at a reasonable level, etc.

Same with gaming up to a point - while less noticeable at 60FPS/60Hz if a CPU is heavily tied up on its physical cores to get a certain level of performance it is noticeable with high frame rate gaming, enabling HT to ease the load off some cores a bit makes a difference to the feel of the game despite not necessarily having an impact on the frame rate. (I'm not entirely sure what is going on underneath there).

EDIT: I'm wondering if Intel's motivations aren't more about protecting their other markets than actually HT having had its day.

 

[Joxeon]

With plenty of Ecores available HT isn’t really needed and if Ecores keep improving at the rate they are then P cores may end up going too.

 

[jigger]

With plenty of Ecores available HT isn’t really needed and if Ecores keep improving at the rate they are then P cores may end up going too.

Then you suffer the latency’s of a mesh topology and require more memory channels.

 

[Deleted User 456458]

Then you suffer the latency’s of a mesh topology and require more memory channels.

You mentioned this mesh nonsense before and were clearly were shown that it's ring topology being used.

Show us how Mesh is being used in ADL/RPL/RPL-S. Not by your gut feeling but by technical documentation that you clearly must have found to be so adamant in your position. Not need to reply with anything but technical findings please.

 

[Emlyn_Dewar]

It's best to just ignore everything jigger says in Intel threads. A broken record of nonsense.

 

[throwaway4372]

All intel/nvidia/amd related threads end up being nonsense, it's like everyone's in a cult.

 

[Dave2150]

It's best to just ignore everything jigger says in Intel threads. A broken record of nonsense.

+1, my forum experience is much more pleasant with just a couple on the ignore list.

 

[Rroff]

With plenty of Ecores available HT isn’t really needed and if Ecores keep improving at the rate they are then P cores may end up going too.

You are always going to have the ability to have more smaller cores which are missing some features and/or cache which will be E cores vs P cores. Or like with Zen 4 and Zen 4C which are effectively a type of E core where the thread director can identify what can run without being penalised on different core types and utilise for best effectiveness which mostly works except with the most complex workloads or where all workloads require the full cache for best performance.

 

[jigger]

You mentioned this mesh nonsense before and were clearly were shown that it's ring topology being used.

Show us how Mesh is being used in ADL/RPL/RPL-S. Not by your gut feeling but by technical documentation that you clearly must have found to be so adamant in your position. Not need to reply with anything but technical findings please.

I have many times…. Google Intel Atom.

 

[ltron]

All intel/nvidia/amd related threads end up being nonsense, it's like everyone's in a cult.

That's what makes being a PC enthusiast exciting .

 

[jigger]

It's best to just ignore everything jigger says in Intel threads. A broken record of nonsense.

Just use the CPU don’t worry about the details. It is what it is.

 

[FredFlint]

I’m looking forward to the new Intel chips. Not had an Intel since 5930K:X99, really hope they put out a platform like that again, 40 gen5 PCIe off the CPU + quad channel RAM at Less crazy prices than the workstation stuff.

 

[Armageus]

I have many times…. Google Intel Atom.

*Yawn*

Intel "Arrow Lake-S" to See a Rearrangement of P-cores and E-cores Along the Ringbus

Intel's first three generations of client processors implementing hybrid CPU cores, namely "Alder Lake," "Raptor Lake," and "Meteor Lake," have them arranged along a ringbus, sharing an L3 cache. This usually sees the larger P-cores to one region of the die, and the E-core clusters to the other...

www.techpowerup.com

And even with Arrow Lake's planned changes.... guess what, still a Ring Bus






Also:
Effect of E-Cores on Ring Clock

Alder Lake – E-Cores, Ring Clock, and Hybrid Teething Troubles

This will be a short post about how Alder Lake’s ring behaves when E-Cores are active.

chipsandcheese.com

 

[jigger]

*Yawn*

Intel "Arrow Lake-S" to See a Rearrangement of P-cores and E-cores Along the Ringbus

Intel's first three generations of client processors implementing hybrid CPU cores, namely "Alder Lake," "Raptor Lake," and "Meteor Lake," have them arranged along a ringbus, sharing an L3 cache. This usually sees the larger P-cores to one region of the die, and the E-core clusters to the other...

www.techpowerup.com

And even with Arrow Lake's planned changes.... guess what, still a Ring Bus






Also:
Effect of E-Cores on Ring Clock

Alder Lake – E-Cores, Ring Clock, and Hybrid Teething Troubles

This will be a short post about how Alder Lake’s ring behaves when E-Cores are active.

chipsandcheese.com

Yawn, did you even read that…

 

[Armageus]

Yawn, did you even read that…

Which part of E cores and P Cores are on a Ring bus = Mesh Bus am I missing?

At least I've bothered to link some diagrams and articles, as opposed to literally making stuff up


Either post evidence or give it a rest (Put Up or Shut Up as it were)