A fascinating theory that hit the rumor-mill, indicates that the company might leverage 5 nm (TSMC N5) carve out larger CCDs with up to 16 "Zen 4" CPU cores. Half of these cores are capped at a much lower power budget, essentially making them efficient-cores. This is a concept AMD appears to be carrying over from its 15-Watt class mobile processors, which see the CPU cores operate under an aggressive power-management. These cores still turn out a reasonable amount of performance, and are functionally identical to the ones on 105 W desktop processors with a relaxed power budget.
Since the "fat" and "slim" cores are functionally identical to each other; AMD need not develop a complex middleware like the Intel Thread Director, and can make do with OS scheduler-level optimizations that it can co-develop with Microsoft or the Linux community, much like it did for older versions of the "Zen" microarchitecture that featured multiple CCXs.
AMD already declared the CPU core counts of its EPYC "Genoa" and "Bergamo" processors to top out at 96 and 128, respectively, a core-count believed to have been facilitated by the larger fiberglass substrate of the next-gen SP5 CPU socket, letting AMD add more 8-core "Zen 4" chiplets, dubbed CPU...
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That's interesting, they haven't bothered trying weld different core architectures together with an extended cache block and unnecessary scheduler functions for them.
Instead they are all the same "fat or big" core (that being relative they are actually little bigger than Intel's E cores and with that 1/3 the size of the P cores, AMD get 3 fat cores to Intel's 1 fat core)
I'm not sure what TPU think they are talking about with "from 15 watt class mobile processors" but they are the same as any other AMD processor just locked to 15 watts, the brain in AMD's chips is able to recalculate the voltage needed at any given power budget, they do this on the fly at 1000Hz, they are not like the dumb CPU's of the past that stick at a fixed voltage no mater what.
If the CPU can have 90% of the Mhz for the given task at 70% of the voltage the CPU's brain will detect that and make the adjustments.
Its what the "Curve Optimiser" is, its your access to fine tune that function, its why you get 90% the performance at 60% the power just by locking the voltage to 60% of TDP, they are over provisioned for the last few 100Mhz and the CPU's brain knows it.
So, with that explained i don't think AMD would do anything at all different with these Zen 4C CCD's, they have a given power budget and that's it.... No different to Zen 4 or even Zen 3. There is no need to treat those cores differently just because there are more of them.