Sounds like higher prices.
This is a good read too:-
https://semiengineering.com/bumps-vs-hybrid-bonding-for-advanced-packaging/
Part taken from that article
Bumps Vs. Hybrid Bonding For Advanced Packaging, The full article is very good.
End of Moore’s Law?
For decades, the IC industry has attempted to keep pace with
Moore’s Law, doubling the transistor density in chips every 18 to 24 months. But starting a decade ago, at 20nm, chipmakers began replacing planar transistors with
finFETs because the gate structure on smaller transistors was insufficient to control current leakage. Transistors continued to leak after devices were turned off, which continued to drain batteries.
Intel introduced finFETs at 22nm in 2011, using what it called a Tri-Gate structure to control leakage at three points in the “off” state, and allow more current to move through when the vertical gates were opened in the “on” state. Foundries followed with finFETs at 16/14nm.
But finFETs also are more complex, driving up design and manufacturing costs. The cost to design a 7nm device is roughly $217 million, compared to $40 million for a 28nm chip, according to Handel Jones, CEO of IBS.
For chips at 7nm and below, the power and performance benefits have started to diminish, leaving many to realize that developing an SoC isn’t always the right solution. “A monolithic die approach forces a one-size-fits-all solution, which is not optimal,” said Walter Ng, vice president of business development for
UMC.
So the industry is looking at alternatives, such as advanced packaging, which promises to address several issues in systems. For example, vendors can break up a large SoC into smaller chiplets and incorporate them in a package, creating an advanced system-level design. “Therefore, the system can be optimized by using the best processor components with an optimum performance/cost process node,” said Xiao Liu, senior program manager from
Brewer Science, in a paper at the IEEE Electronic Components and Technology Conference (ECTC).
For this and other applications, there are several ways to integrate chips in packages, such as fan-out. In one example of fan-out, a DRAM die is stacked on a logic die in a package.
2.5D is another option. In 2.5D, dies are stacked on an interposer, which incorporates
through-silicon vias (TSVs). Another option is
3D-ICs, where logic-on-logic or logic-on-memory are stacked in a 3D-like package.
None of these technologies will replace traditional SoCs, but they can be used to supplement them. In fact, leading-edge chips often are incorporated in advanced packages. The package boosts the performance of the design.
Going forward, there is some uncertainty. Chipmakers are ramping up 5nm chips, with 3nm and beyond in R&D. It’s hard to predict when, but at some point traditional chip scaling will falter. When that occurs, the industry will need help from packaging to stay on the roadmap. That’s why the chiplet model is important. In one futuristic scenario, vendors may integrate chiplets in 3D-like packages, creating system-level designs that mimic a traditional SoC.
Nonetheless, there are many packaging options today with bumps and other interconnect schemes. Now, hybrid bonding is in the mix. So what’s the best option?