Intel has already confirmed the use of Level 4 caches for its upcoming System on a Chip codenamed Meteor Lake. This was first reported by
Phoronix in the recent Linux patches. Other than confirming the return of L4 cache on processors, similar to eDRAM that we had on the Intel Broadwell platform, the details on Meteor Lake implementations are missing.
As it turns out, Intel had already filed a patent that may explain the use of such cache. According to the patent from December 2020, the ‘next-generation SoC architecture’ aka Meteor Lake is to feature ‘on-package caches’. In other words, the Adamantine cache would be part of the base tile that could be accessed by any of the building blocks of next-gen SoC.
Meteor Lake will fully embrace the hybrid architecture combining five different tiles: CPU, SoC, GPU, I/O and base tile. The Adamantine cache would offer much faster access time than any typical cache like L3, which is typically part of the CPU tile.
As explained by Intel, the main purpose of L4 cache is to improve boot optimization and increase security around the host CPU. Furthermore, the L4 cache would preserve the cache at reset, leading to improved loading times that would otherwise have to go through all boot/reset cycles.