IIRC, reports were that AM5 wasn't initially going to use DDR5.
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AMD demonstrates Ryzen 9 5900X prototype with 3D V-Cache stack chiplet design
- Thread starter RavenXXX2
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IIRC, reports were that AM5 wasn't initially going to use DDR5.
I haven't seen any such reports. It's Alder Lake which will support both DDR4 and DDR5.
I might be confusing it with PCIE 4, as I'm sure I've read some reports that Intel is going PCIE 5 with their next gen, and AMD are sticking with PCIE 4.
In theory, AMD would have it (relatively) easy to support some flavour of Zen4 on AM4 - that is Zen 4 with DDR4 - with their CCD + IO approach. Assuming none of the ~500 extra pins of AM5 are actually required by just the Zen4 CCD.
PCIe 5.0 on the other hand would mainly be marketing on desktop (and mobile, although there are always people who claim they really need PCIe 4.0 with Renoir or Cezanne laptops).
Might be useful for servers and ThreadRipper though as long as it's not too power hungry.
For server there is some speculation that multiple layers of 3D cache might make sense, since apparently TSMC have talked about multiple layers. Some of the supercomputer projects might be able to afford that.
PCIe 5.0 on the other hand would mainly be marketing on desktop (and mobile, although there are always people who claim they really need PCIe 4.0 with Renoir or Cezanne laptops).
Might be useful for servers and ThreadRipper though as long as it's not too power hungry.
For server there is some speculation that multiple layers of 3D cache might make sense, since apparently TSMC have talked about multiple layers. Some of the supercomputer projects might be able to afford that.
https://hothardware.com/news/amd-ryzen-am5-cpus-2022-intel-z790-raptor-lake-q3
um...no.
Just because 1 single leak from a guy with no prior reputation says "AM5 2022 Q2" doesn't mean the V cache Zen 3 chips are on AM5. Q2 can literally mean 6 months, and if the rumoured Alder Lake performance numbers are true, there is zero chance in hell AMD are going to sit and wait for 6 months to counter it when they literally showed existing technology can be boost by 15% just by slapping some cache on it.
I'm calling it now: Ryzen 5000 will see some limited run refreshes - another XT line? - using the V cache to take the performance crown back from Alder Lake. They'll be announced and demoes at CES and available about February. That serves to get TSMC's stacking ultra reliable (allegedly 1 layer is trivial already) ready for volume production of Zen 4 chiplets, and also for memory manufacturers to flood the market with DDR5, let the performance and price stabilise and basically let Intel early adopters pick up the bill.
Is it even speculation? Sounds more like crossing of wires and unfounded assumptions.
Will 15% be enough against Alderlake though especially with those supposed ST numbers?
And vice versa, release Zen 3 cores paired with DDR5 IO controller early on AM5
It’s more than a 15% gain. IIRC the 15% was from a slide that averaged out half a dozen games.
Alder Lake Cinebench R20 Leak is 810 Points ST.
5950X ST is about 650, +15% would = 748, so 9% short.
12900K R20 MT: 11600
5950X R20: 10500, + 15% = 12,075.
Its Zen 4 that Alder Lake is up against tho and the performance increase of that is rumoured to be significant, whatever that means, its going to be higher than Zen 3D.
I guess that depends if the V-cache translates into production workloads as well as it does games as there was only gaming benchmarks shown in the teaser.
For floating point workloads, which Cinema 4D and Blender, ecte.... are, it should translate.
Its probably an indication that if true this Alder Lake performance should also translate to gaming.
However, two things.
#1, if there is some AVX hackery going on here to explain that performance in Cinebench it will not translate to games.
#2, as well all know Gaming is sensitive to intecore communication, Despite Rocket Lake having a 20% higher IPC than Coffee Lake the gaming performance is at best identical, because the Ring Bus in Rocket Lake is no faster than the one in Coffee Lake.
Now here is the thing, a lot of people don't realise this but Zen 3 intecore communication is significantly faster than Intel's Ring Bus, that's why in some games where the CPU really is the one doing all the work you're seeing up to 35% higher performance on Zen 3 vs Rocket / Coffee Lake.
To add, the IPC on Zen 3 is only about 15% higher than Zen 2, which was pretty high at 10% higher than Coffee Lake.
Gaming performance is up to 55% faster on Zen 3 vs Zen 2, that's the power of Zen 3's new Intercore mesh thingy....
PS: that's what happens when a competent Semi Conductor designer looks at where they are weak and fix it
Gaming performance is up to 55% faster on Zen 3 vs Zen 2, that's the power of Zen 3's new Intercore mesh thingy....
PS: that's what happens when a competent Semi Conductor designer looks at where they are weak and fix it
We've all seen how Intel has started massaging benchmarks since they lost the performance lead (including claiming higher gaming performance from the higher specced graphics card in a system and pretending it's down to their CPUs), so I'll not trust any numbers they put out until I see independent benchmarks from trusted reviewers.
really, intel did that. if that kind of thing is going on then its just awful from a very wealthy large company
Isn't the most cache friendly (or dependent) workload something like 7zip?
So for anyone whose productive software usage is archiving files all day Zen+3D cache might be just the ticket.
I'm sure there are other workloads too, of course.
Gamers Nexus spoke with understated excitement at the massive gains the v cache design will bring to cache-loving workloads, code compilation was one example. The average 15% boost we saw in gaming is probably "just" reducing the need to bounce around chiplets (it was a 12 core prototype demonstrated), but for any task that actually makes use of cache explicitly, the gains could be massive.
And we're not just talking desktop Ryzen, the v cache is an addition to the chiplets, so there's no reason why v cache couldn't or wouldn't end up on Threadripper and EPYC. That, I think though, is a Zen 4 thing.
And we're not just talking desktop Ryzen, the v cache is an addition to the chiplets, so there's no reason why v cache couldn't or wouldn't end up on Threadripper and EPYC. That, I think though, is a Zen 4 thing.