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*** AMD ThreadRipper ***

As far as 32 cores on the Threadripper platform goes, my own feeling is that it looks very unlikely that is possible. This is based on the following reasoning, I'm just an interested observer. I have no inside knowledge.

Each Zen die has 2xDDR4 channels and 32xPCIE lanes (actually described by AMD as 'two by sixteen links').

For EPYC with it's a 4 die MCM with 8 channel DDR4 and 128 PCIE lanes. Two memory channels and 32 PCIE lianes are routed to each die on the MCM. For the two socket systems 16 of these 32 PCIE lanes are repurposed as the Infinity Fabric link to the corresponding die on the neighbour socket. The on-socket Infinity Fabric links between the four dies on the MCM are using a custom PHY and cannot be repurposed for off-socket I/O. This is all from AMDs EPYC presentations.

All the off-socket I/O for EPYC goes through the 4.094 pins in the SP3 socket
For Threadripper the spec is 64 PCIE Lanes and 4 DDR4 memory channels through the 4.094 pins TR4 socket. Same number of pins, so what gives?

We know that the SP3 and TR4 sockets are physically identical, but clearly SP3 has far more I/O than TR4. So it seems that the SP3 & TR4 sockets are electrically different, To provide the I/O for Threadripper TR4 only needs to actually connect two of the dies on the MCM the the motherboard. This makes sense., Rather than design a whole new socket for a very niche market AMD has repurposed the already developed server socket and MCM package.This keeps costs down for AMD, and by only electrically connecting about half of the socket the motherboard costs can stay under control.

So it doesn't really matter whether the two 'extra' dies on the Threadripper MCM are capable of working or not I strongly doubt that they are even connected through the TR4 socket.

As for wether the 'extra' dies are 'dummy' ones just for structural integrity of the MC or not. I personally doubt it, but for only one reason. If they were just raw, unprocessed silicon I would have expected Roman to notice that right away when he de-lidded it. As for wether they are dies that failed somehow; if I'm right and the socket only connects to two of the dies then it would mean that AMD would have to get 'lucky' with the failed die or dies being the ones that aren't connected.

This does leave open a couple of questions.

What exactly AMD are doing to produce Threadripper? I wouldn't be surprised if AMD are just pulling some MCMs from production and putting them through a different validation process for Threadripper. They know that the server ramp-up is likely to be slow at first and it's better to get processors sold than sitting on shelves. It's also very good PR particularly if you can deliver something you know the competition can't match.

The other question is what happens if you put Threadripper in a fully-connected SP3 socket? That's an interesting one, but it's a whole different topic.
 
Tim Preston said:
As far as 32 cores on the Threadripper platform goes, my own feeling is that it looks very unlikely that is possible. This is based on the following reasoning, I'm just an interested observer. I have no inside knowledge.

Each Zen die has 2xDDR4 channels and 32xPCIE lanes (actually described by AMD as 'two by sixteen links').

For EPYC with it's a 4 die MCM with 8 channel DDR4 and 128 PCIE lanes. Two memory channels and 32 PCIE lianes are routed to each die on the MCM. For the two socket systems 16 of these 32 PCIE lanes are repurposed as the Infinity Fabric link to the corresponding die on the neighbour socket. The on-socket Infinity Fabric links between the four dies on the MCM are using a custom PHY and cannot be repurposed for off-socket I/O. This is all from AMDs EPYC presentations.

All the off-socket I/O for EPYC goes through the 4.094 pins in the SP3 socket
For Threadripper the spec is 64 PCIE Lanes and 4 DDR4 memory channels through the 4.094 pins TR4 socket. Same number of pins, so what gives?

We know that the SP3 and TR4 sockets are physically identical, but clearly SP3 has far more I/O than TR4. So it seems that the SP3 & TR4 sockets are electrically different, To provide the I/O for Threadripper TR4 only needs to actually connect two of the dies on the MCM the the motherboard. This makes sense., Rather than design a whole new socket for a very niche market AMD has repurposed the already developed server socket and MCM package.This keeps costs down for AMD, and by only electrically connecting about half of the socket the motherboard costs can stay under control.

So it doesn't really matter whether the two 'extra' dies on the Threadripper MCM are capable of working or not I strongly doubt that they are even connected through the TR4 socket.

As for wether the 'extra' dies are 'dummy' ones just for structural integrity of the MC or not. I personally doubt it, but for only one reason. If they were just raw, unprocessed silicon I would have expected Roman to notice that right away when he de-lidded it. As for wether they are dies that failed somehow; if I'm right and the socket only connects to two of the dies then it would mean that AMD would have to get 'lucky' with the failed die or dies being the ones that aren't connected.

This does leave open a couple of questions.

What exactly AMD are doing to produce Threadripper? I wouldn't be surprised if AMD are just pulling some MCMs from production and putting them through a different validation process for Threadripper. They know that the server ramp-up is likely to be slow at first and it's better to get processors sold than sitting on shelves. It's also very good PR particularly if you can deliver something you know the competition can't match.

The other question is what happens if you put Threadripper in a fully-connected SP3 socket? That's an interesting one, but it's a whole different topic.
Click to expand...

As you say the TR and SP sockets are identical, the IO value difference is because only 2 CCX clusters are operating on Threadripper rather than the Socket being limited to 2 CCX cluster valued IO.

Unlock 3 CCX clusters and you get 3 CCX value of IO, Unlock 4 CCX..........................
 
Tom B said:
Why the hell do these top end boards still have PS/2 connectors??
Click to expand...

PS/2 has much lower latency that USB, so is the preference method of input for pro gamer and a lot of keyboards only offer nkro over PS/2. Plus, a lot of professional level equipment uses PS/2 -like my graphics tab for instance.
 
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