AMD Zen 2 (Ryzen 3000) - *** NO COMPETITOR HINTING ***

[humbug]

I suspect that the next gen Intel desktop CPUs will be on a 14nm process but with improved cores. They could still have a hand in this fight yet, but at the cost of being well behind on performance/watt.
That strikes me as an opportunity for AMD; push hard on mobile, utilising that perf/watt where it is most relevant, and getting a foot through the door with OEMs since they are begging for improved performance at very low power. However, AMD seriously need to sort out idle power draw for that market.

I think there are limits to mow many +'s you can keep adding onto a process node and i think Intel have reached that limit, ever increasing clocks are just not an option anymore IMO Intel have reached those limits.
They may do a 10 core, if i remember correctly its even been rumoured and while that perhaps was their intent now i think they are just not going to do it as doing it shrinks wafer yields, makes them quite large and inefficient and still way short of AMD's no doubt much cheaper and much faster 3800X 16 core.

10 is also the limit of the Ring Bus that gives Coffeelake its performance, that already only being the same as Zen+, the Mesh that you find in Skylake-X has 10% less IPC so no point looking there......

 

[TrixX]

On the topic of Threadripper, do we think it too has its own separate IO die?
Logic says yes, since Epyc and Ryzen have 8 and 2 channel memory, whilst Threadripper has 4, however, one of the previous posts mentioned Ryzen perhaps having 4 memory controllers, 2 of them being redundant(?). Is this likely?
On a similar theme, I don't see AMD purposely laser cutting functional cores for segmentation even if yield is unreal, so old school unlocking of redundant cores may well be possible. That being said, I guess we might have seen it in the first 2 generations if it was possible, though I suppose that an 8c chiplet might offer more scope in that regard.

EPYC's memory controller is on the I/O die so it's purely down to how many channels that supports rather than each individual CCX. So ThreadRipper will just have 4 of the possible 8 channels active. There's a possibility for 128c ThreadRipper but I doubt it'll happen this generation, similar to how the 32c ThreadRipper didn't surface until the 2nd Gen ThreadRipper's. Going to be very interesting to see the ThreadRipper's performance with the EPYC's results so far.

 

[humbug]

How long would Cinbench run with 128 cores 256 threads? 1 second?

click..and its done!

 

[d_brennen]

Back when people were saying no IO die for Ryzen I said it was against the Zen philosophy of using the same chips top to bottom... I suspect the IO die at least shares a lot with the Epyc IO die. Haven't seen anyone do a size comparison with pixel measurements yet, wouldn't be surprised if it were the same silicon binned/fused for desktop use

 

[Sargatanas2511]

Back when people were saying no IO die for Ryzen I said it was against the Zen philosophy of using the same chips top to bottom... I suspect the IO die at least shares a lot with the Epyc IO die. Haven't seen anyone do a size comparison with pixel measurements yet, wouldn't be surprised if it were the same silicon binned/fused for desktop use

Comparing the I/O die on the Epyc they showed off to the I/O die on the Zen 2 it was clearly significantly smaller on Zen. It had probably had a lot of memory controllers and such that are not needed on the desktop platform cut out and therefore is much smaller.

https://www.dropbox.com/s/ahk75f64msqjyo7/IO die.PNG??raw=1

An extremely crude paint comparison I just put together.

 

[andy_mk3]

Ignoring a couple of members makes this thread a whole lot more bearable. Just ignore them and don't respond to their rubbish, they'll get bored and go away.

How long would Cinbench run with 128 cores 256 threads? 1 second?

click..and its done!

Well this is with 112 threads (Skip to 7:55)

 

[humbug]

Thanks, double that then ^^^ fast, really fast.

Back when people were saying no IO die for Ryzen I said it was against the Zen philosophy of using the same chips top to bottom... I suspect the IO die at least shares a lot with the Epyc IO die. Haven't seen anyone do a size comparison with pixel measurements yet, wouldn't be surprised if it were the same silicon binned/fused for desktop use

AdoredTV made a video about this, he thinks the IO dies are made up of quadrants with each quarter having its own cache, IO and two channels of memory, the full die would be for the 8 channel EPYC, cut it in half for quad channel Threadripper and one quarter for Ryzen.

They are actually all the same die but with ones that have faulty quadrants being used for Threadripper/Ryzen...

If i find the video i'll post it.

 

[lltfdaniel]

This link below will start at 7:55 straight away and thanks Andy for the youtube link.

https://youtu.be/VJawYtS_MlE?t=475

I tried to use the media thingy where you can just watch the video in this thread but it does not work as in starting at 7:55 which is why i gave the link only.

 

[andy_mk3]

This link below will start at 7:55 straight away and thanks Andy for the youtube link.

https://youtu.be/VJawYtS_MlE?t=475

Hah, thanks. I did use that link but the time stamp gets removed when embedded.

 

[lltfdaniel]

Hah, thanks. I did use that link but the time stamp gets removed when embedded.

Yeah that's why i did it like that i don't know why but o well.

 

[humbug]

Thanks, double that then ^^^ fast, really fast.



AdoredTV made a video about this, he thinks the IO dies are made up of quadrants with each quarter having its own cache, IO and two channels of memory, the full die would be for the 8 channel EPYC, cut it in half for quad channel Threadripper and one quarter for Ryzen.

They are actually all the same die but with ones that have faulty quadrants being used for Threadripper/Ryzen...

If i find the video i'll post it.

 

[Journey]

There's a possibility for 128c ThreadRipper but I doubt it'll happen this generation,

Sorry to say that is not the case, as much as I've love it to be true. EPYC (Rome) tops out at 64c/128t, and since TR is just a hobbled EPYC, it could only be a maximum of 64c, if I was putting money in it I'd say they will choose to go no higher than 48c/96t for now.

 

[Potatowithearsontheside]

Thanks, double that then ^^^ fast, really fast.



AdoredTV made a video about this, he thinks the IO dies are made up of quadrants with each quarter having its own cache, IO and two channels of memory, the full die would be for the 8 channel EPYC, cut it in half for quad channel Threadripper and one quarter for Ryzen.

They are actually all the same die but with ones that have faulty quadrants being used for Threadripper/Ryzen...

If i find the video i'll post it.

The Ryzen IO die is definitely bigger than one quarter of the Rome die. There must be something additional on it.
Not enough room for the smallest iGPU, or for L4 cache.

I think there are limits to mow many +'s you can keep adding onto a process node and i think Intel have reached that limit, ever increasing clocks are just not an option anymore IMO Intel have reached those limits.
They may do a 10 core, if i remember correctly its even been rumoured and while that perhaps was their intent now i think they are just not going to do it as doing it shrinks wafer yields, makes them quite large and inefficient and still way short of AMD's no doubt much cheaper and much faster 3800X 16 core.

10 is also the limit of the Ring Bus that gives Coffeelake its performance, that already only being the same as Zen+, the Mesh that you find in Skylake-X has 10% less IPC so no point looking there......

We should differentiate the architecture from the process node, as Intel have stated they've begun doing.
That means that they have found a way to offer better cores and then port to to better node once yields and performance improve. That suggests that the Cove cores will be pretty decent, usable with 14nm process, but only see full benefits with 10nm or 7nm process nodes. In other words, they can get the performance but they can't get the power savings just yet.
I suspect another very good 14nm product to come, but perhaps not til 2020. After that they'll certainly go aggressive on process nodes IMO.

 

[smilingcrow]

Sorry to say that is not the case, as much as I've love it to be true. EPYC (Rome) tops out at 64c/128t, and since TR is just a hobbled EPYC, it could only be a maximum of 64c, if I was putting money in it I'd say they will choose to go no higher than 48c/96t for now.

It was only with TR2 that they jumped to 32C and they had reason to as it put them ahead of Intel.
I don't see the same need now as I can't see Intel competing with a 32C Zen 2 soon.
So why would AMD release higher than 32C at the same price as the current 32C or even at all this year possibly?
It's one thing to offer good value but another to price way below market value
But as TR is low volume they could offer it cheaply partly as a goodwill gesture and also to keep the platform volumes high enough to make sense to board makers.

 

[smilingcrow]

Intel are used to massive margins on retail desktop CPU's and at very high volume, this subsidises OEM markets where to keep AMD out they practically give their chips away.

Surely the real profit is with OEM chip sales as that is the where the real volume is not retail!
Of course the OEMs aren't paying tray price as they are buying millions per year.
If retail sales are so important why did Intel make such large profits last year when AMD has done so well at retail?
Because OEM is where the money is.

 

[Minstadave]

Surely the real profit is with OEM chip sales as that is the where the real volume is not retail!

Indeed.

 

[Stephanie Peterson]

The way these chiplets can be salvaged from defective dies means AMD are going to get almost every chiplet they make out of even a new 7nm process.
They will need to build up stocks of damaged chiplets with say 1 damaged core making it say a 6 core or 3 making them a quad for instance - these can become 12 core ryzen 7s for those with say 6 working cores ( or of course ryzen 3s)
The ones only able to work effectively as quads will become.. i dunno.. APU's maybe? or more likely Althon cheepos.

Utter genius design and a huge money saves compared to intels monolithic approach.

Big question for me is just what is in that huge 14nm IO die? could it have a massive 3rd level cache?

 

[LePhuronn]

Big question for me is just what is in that huge 14nm IO die? could it have a massive 3rd level cache?

A crazy idea I've heard (forget the source now) was it has a mirror cache for every chiplet connected to it so rather than chiplet X having to make a few hops to get something from chiplet Y it can just retrieve that data from the corresponding mirror cache on the I/O die (if it's up-to-date). Cuts down on latency everybody's been a bit cautious about.

 

[Scramz]

Interesting predictions and talk on IPC.

I am not of the same view though, I think clock was slower than 4.6Ghz.

 

[Stephanie Peterson]

Yeah that would make sense, would cut latency a lot and be cheep and easy to manufacture.

Now i wonder what they have planned for AM5 when it comes out in a couple of years? Quad channel DDR 5 ram capability perhaps...
Prob stick with dual on the consumer platform but heck what a beast the APUs would be if they were given quad DDR5 bandwidth.