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AMD Zen 2 (Ryzen 3000) - *** NO COMPETITOR HINTING ***

humbug said:
How? depends what they are measuring, Rome has 2MB L3 per core

By that measure the 8 core would have 16MB, the 12 core 24MB and the 16 core 32MB

which is whats listed.
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I did post this a few pages back but I'll quote myself as it may have been missed..
Murphy said:
AMD have stated that the µOP cache has been enlarged (to what they've not said), the size of the cache on Zen was 2,048 entries (2MB per core), each entry is one addressable memory location so technically they could've increased those without increasing the amount of cache but that would mean the memory would be divided rather oddly (IIRC most memory typically address 1024 byte sections at a time).

(Heinz)
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alec said:
There is no mechanism to directly access L3 of another CCX.
What is misquoted as cross CCX latency in tomshardware is a round trip to DDR4 and back. (check own L3, check main memory, flush other CCX L3 to memory, retrieve data). That is why memory speed affects this metric a ton.

Infinity fabric between two CCX exists so that they can share the memory controller. There is no cross CCX communication except going to shared memory controller (on another chips memory controller in case of Threadripper and Epyc).
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That's not entirely correct, all the L3 attached to each core is handled as a single large pool (Link 1, 2), the memory speed effects latency because IF (the data fabric part) and the memory controllers share the same clock domain (data crossing a clock domain introduces latency), and lastly there are 2 four core CCX's per die so you get a latency jump mainly when passing data between physically separate dies, having said that the latency issue has been blown out of proportion IMO, when testing was done Ryzen was found to have lower latency than Intel between cores on the same die but higher when it was between dies (40ns vs 80ns for the former and 80ns vs 140ns for the latter), neither of which you should really notice unless you're constantly bouncing data between cores.
 
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Silent_Scone said:
They're free to disclose anything they don't agree with in the reviews, so it's down to the reviewer, mostly. If the narrative makes sense, then they'll go with the flow. Being humble is the best policy, especially when it comes to the deeper stuff.
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Yes, I agree some however some are not very forth coming with this sadly.

Hopefully the board you are getting is better than the last dev board I had on my bench, it had so many wire mods on it, it looked like snakes on a plane :D
 
~>Dg<~ said:
tbh this forums is pro amd. look at some of the thread titles. amd this that . but if you title it intel faster than amd it would be changed or removed.

how many intel fans have changed to intel for eg. a lot of people here just cant post without biased. then if you say that its because you are biased lol.
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Go back a few years (two or three) and every CPU thread on this forum was pro Intel. You were excoriated (love that word) for even thinking of buying anything else. It was only Ryzen 1xxx that turned that around. Still quite a few people though who have ignored that. It is only because AMD are thinking out of the box and their stuff works that they have attracted all the attention on here.
 
humbug said:
an excrement
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humbug said:
excrement excrement
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To be honest, I wasn't expecting so low wording and expressions from a user who I had generally respected a lot... :o

Silent_Scone said:
I believe I said Zen wouldn't do 3866 on the memory side, and it didn't. Still doesn't, in fact on current gen. Let's not do this again Humbug, just engage in the speculation and discussion, please.
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When someone falls that low, I wouldn't think that any possible discussion would be possible from now on.
 
xtremedetailz said:
Just admit that you was wrong and then everyone will stop badgering you about it and get back on topic.
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Wrong about what? I've not seen a single HCI memtest result posted to prove otherwise...

Perhaps I'm just eager to share things with individuals when I can't, but they're not far round the corner. Just seems there are some extremely bitter individials, too.
 
4K8KW10 said:
To be honest, I wasn't expecting so low wording and expressions from a user who I had generally respected a lot... :o
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excrement poster is a forum friendly way of saying ####poster.

You weren't around to see that ####posting.
 
Murphy said:
That's not entirely correct, all the L3 attached to each core is handled as a single large pool (Link 1, 2), the memory speed effects latency because IF (the data fabric part) and the memory controllers share the same clock domain (data crossing a clock domain introduces latency), and lastly there are 2 four core CCX's per die so you get a latency jump mainly when passing data between physically separate dies, having said that the latency issue has been blown out of proportion IMO, when testing was done Ryzen was found to have lower latency than Intel between cores on the same die but higher when it was between dies (40ns vs 80ns for the former and 80ns vs 140ns for the latter), neither of which you should really notice unless you're constantly bouncing data between cores.
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Yes, I agree with everything, except that a core on one CCX can read from L3 of another CCX directly. Even in your quoted example (a very thorough review), latency between dies is for Zen is higher than latency to main memory.
How and why could that be if not because it goes through the main memory, using DDR as LLC (last level cache)
 
Silent_Scone said:
We've done this before, dude. Couple this with the fact nobody has yet to get 3866 stable, which you proclaimed not to be true, either, I don't think anything else needs to be said. Let us move on.

https://forums.overclockers.co.uk/posts/30430250/
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You sound like you're actually trying to convince yourself - don't think anyone else will be swayed by your revisionism. You have a proven record.
 
alec said:
Yes, I agree with everything, except that a core on one CCX can read from L3 of another CCX directly. Even in your quoted example (a very thorough review), latency between dies is for Zen is higher than latency to main memory.
How and why could that be if not because it goes through the main memory, using DDR as LLC (last level cache)
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I'm not sure where you're getting the idea that latency between dies is higher than it is to main memory, could you be mixing up ns with ms?
 
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