One advantage of the chiplet design is they could easily spin DDR4 / PCI-E 4 and DDR5 / PCI-E 5 versions with different IO controllers made on an inexpensive node. CCX chiplets can be common to both but importantly, AMD don't have to commit the expenisve CCX chiplets to either platform giving them great supply chain flexibility.
I don't see why they'd do that, though. It'd be confusing for the average end user and more expensive for them.
PCIe 5.0 sees some latency improvements, doubling of bandwidth again, and improved signal integrity, but it's supposedly less of a change than 3.0 to 4.0, in terms of engineering and software etc. I also don't see why the memory controller couldn't function as both DDR4 and DDR5. They're not completely different memory standards. One is a logical extension of the other.
To be clear, the scheduling update is in the May 2019 update for Windows 10 v1903. Stock v1903 doesn't include it.
Basically keep your copy of Windows 10 up to date to get it.
Yeah, I'm aware. But wasn't mindful of it when I wrote that. I did mean 1903 including the AMD scheduler improvement.
I suppose it will be interesting to see what uplift Zen 2 gets from it, as supposedly all benches so far have been on v18xx.
I'm mainly interested to see what the difference ends up being once mitigations are applied to the Intel CPUs ... but I think we'll have to look around for those.