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*** AMD "Zen" thread (inc AM4/APU discussion) ***

Silent_Scone said:
I just think you don't have the capacity to read what you're quoting (correctly). I've explained it to you already.

I also have the board here...not much more to say.
Click to expand...

I am just truly stunned you actually believe you know more than the 3 review sites. I`ll have whatever you are smoking. Anandtech also have reviewed the feature on kaby lake and agree with the 3 sites I have linked to already.

so far your argument, your word against mounting evidence , amounts to little.
 
As fun as this is, let's bring it to a close. Why don't you explain to everyone how you think the AVX offset should be used in conjunction with overclocking?

That way instead of me wasting my time, you can hang yourself proverbially by doing so
 
Hold up guys, I only suggested that AMD may fall behind in AVX heavy code (my speculation), as Intel have the historical advantage here. AMD will likely have similar power management to cores that are running AVX code exclusively, as it will likely work their uArch as hard as it does Intel's.

Intel will probably have a theoretical advantage to how wide their registers are, hence my inference that "new" benchmarks may show them pull ahead again despite nothing in hardware changing...

Peace
 
Silent_Scone said:
As fun as this is, let's bring it to a close. Why don't you explain to everyone how you think the AVX offset should be used in conjunction with overclocking?

That way instead of me wasting my time, you can hang yourself proverbially by doing so
Click to expand...

highly fun - and whats overclocking (as user set function) got to do with default settings?

everything beyond default - is user controlled and your own risk.
 
CAT-THE-FIFTH said:
I think it was something on how the FPU is organised - IIRC it has two 128 bit units which can technically do 256 bit operations but splits it across two units. AFAIK,Intel uses 256 bit units.
Click to expand...

From what we've seen so far, that could go either way in terms of performance

Harlequin said:
highly fun - and whats overclocking (as user set function) got to do with default settings?

everything beyond default - is user controlled and your own risk.
Click to expand...

I wouldn't worry, you're not the first or last person who doesn't understand how the offset function works. That's not meant with any disrespect.

https://hardforum.com/threads/msi-x99a-xpower-gaming-titanium-lga2011-v3-review-h.1906302/

Even Dan at HardOCP was lost.
 
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opethdisciple said:
When are Intel meant to be releasing the next consumer 6 core chips (cannon lake)?

I.e the chips they are replacing the current Kaby Lake i7?
Click to expand...
The 6-core chips are codenamed Coffee Lake, and they're due in 2018.

Cannonlake is a die shrink of Kaby Lake that's due in late 2017 but will only appear in mobile chips. Basically it is not of interest to desktop users (similar to Broadwell). Icelake, a new architecture on 10 nm that at least in theory should be released in desktop variants, is also due in 2018. I would not be the least bit surprised if that date slips.
 
So am I reading the last page right?

This an about demanding AVX workload needing management to keep the CPU within intended operating specifications. This is being put as evidence of a problem with AVX implementation, from the perspective of using the processor outside of spec.
In 1151 engineers have provided a feature which allows the overclocker to specify 2 overclocks. This is through a negative offset multiplier for the power hungry AVX workloads which will also trigger a slight voltage reduction (-to the AVX silicon only?) preventing unnecessary power use and heat while those instructions are in use.
 
Silent_Scone said:
From what we've seen so far, that could go either way in terms of performance



I wouldn't worry, you're not the first or last person who doesn't understand how the offset function works. That's not meant with any disrespect.

https://hardforum.com/threads/msi-x99a-xpower-gaming-titanium-lga2011-v3-review-h.1906302/

Even Dan at HardOCP was lost.
Click to expand...

so let me get this right - you , as a forum user , have more `understanding` how it works , than all of the review community?

really?

or , your talking ****.
 
eddyr said:
So am I reading the last page right?

This an about demanding AVX workload needing management to keep the CPU within intended operating specifications. This is being put as evidence of a problem with AVX implementation, from the perspective of using the processor outside of spec.
In 1151 engineers have provided a feature which allows the overclocker to specify 2 overclocks. This is through a negative offset multiplier for the power hungry AVX workloads which will also trigger a slight voltage reduction (-to the AVX silicon only?) preventing unnecessary power use and heat while those instructions are in use.
Click to expand...

It's been around awhile on server platforms, although the offset register is non adjustable there. So it's not simply when used out of spec. It's because Intel acknowledged the current that the instruction set can pull under certain conditions.

That tells you all you need to know about the potential it has for harm in conjunction with overclocking.

Harlequin said:
so let me get this right - you , as a forum user , have more `understanding` how it works , than all of the review community?

really?

or , your talking ****.
Click to expand...

Without trying to toot my own trumpet.

Yes. I take it you bothered to read Dan's reply?
 
eddyr said:
So am I reading the last page right?

This an about demanding AVX workload needing management to keep the CPU within intended operating specifications. This is being put as evidence of a problem with AVX implementation, from the perspective of using the processor outside of spec.
In 1151 engineers have provided a feature which allows the overclocker to specify 2 overclocks. This is through a negative offset multiplier for the power hungry AVX workloads which will also trigger a slight voltage reduction (-to the AVX silicon only?) preventing unnecessary power use and heat while those instructions are in use.
Click to expand...

server (and now desktop) cpu`s which use AVX, has the feature to reduce cpu speed automatically , and this is set to auto by default. once the cpu goes past power loading it throttles back. in fact desktop boards do this when using AVX , its only of recent that a UEFI update exposed the auto function to allow it to be user modified (all skylake boards would run AVX-256 instructions in auto mode)
 
CAT-THE-FIFTH said:
I think it was something on how the FPU is organised - IIRC it has two 128 bit units which can technically do 256 bit operations but splits it across two units. AFAIK,Intel uses 256 bit units.
Click to expand...

Thats Bulldozer/Piledriver, or at least it is in 8 thread hyperthreaded mode, 4 thread combined its 256Bit...... one of its problems, isn't Zen using 256Bit FPU's?
 
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