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Intel Core Ultra 9 285k 'Arrow Lake' Discussion/News ("15th gen") on LGA-1851

cebri said:
Apparently L3 cache latency is… abysmal. The more intensive the game is on the L3 the worse it performs.

It has been reported Lunar Lake has LionCove+ with a better memory hierarchy.
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I assume you mean the comments from David Huang? As he discusses the cycle count "The L3 latency of Luna Lake and Rapter Lake is about 55 cycles, while Arrow Lake (265K) is about 73 cycles and Meteo Lake (155H) is 80 cycles."

I have also seen counters to this, which point to the IMC adding ~15ns.

Unless you are an Intel engineer, id say most while good guesses are a finger in the wind.
 
ooStevo said:
In all seriousness, it's something to do with the algorithm. If you have an open 'surprise/omg' mouth,it apparently generates more clicks. Not from me though, I'm retarded enough as is
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Yeah, any mid to large channel AB tests multiple thumbnails for every video, as well as different titles. They're doing these stupid faces because that's what gets clicked. The face on there makes sense I guess, humans are super tuned to notice faces and seeing someone you know on the thumbnail tells you what you're going to get to an extent, but I don't understand quite why the weird expressions work.
 
Mr Jack said:
Yeah, any mid to large channel AB tests multiple thumbnails for every video, as well as different titles. They're doing these stupid faces because that's what gets clicked. The face on there makes sense I guess, humans are super tuned to notice faces and seeing someone you know on the thumbnail tells you what you're going to get to an extent, but I don't understand quite why the weird expressions work.
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It's basically OMG you have to see this!!!!! So if you are inclined in a certain subject,your mind will think,hmmmmmm, this could be more info for the brain,he/she looks surprised,it must be good!!! Turns out a load of pish.
 
Robert896r1 said:
They need to maintain this efficiency, fix the scheduling, latency issues and next gen should perform well. ~230w for 47k is pretty sick and it’s not voltage floored.
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From the efficiency standpoint is very impressive if you consider what a 14900K would be used to score 47K (400-450W). Also when you take into account the 9950X, as an example see my 9950X with just PBO enabled pulls 293W in this example for 45K

h6oDqQ1.jpg

When I normally test, I normally measure it directly from the wall so I am looking forward to testing this and seeing where it ends up. On a small side note, I have my 9950X just shy of 50K in R23 at the moment and that's pulling over 500W's from the wall.
 
g67575 said:
Is the 20a process really dead, I wonder? Are those foundries gonna remain idle for another year?
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18a is supposed to come in 2026 for desktop.

20a is 99% a dead socket
Intel don't build a specific foundry for one cpu model and then delete it and build a new on when they are done.


Who actually makes them anyway I thought TSMC did? and intel just packages the chip( which doesn't mean plastic and cardboard.

google is full of articles like saying they cancelled 20a and used someone else probably tsmc to build the chiplets
 
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arknor said:
18a is supposed to come in 2026 for desktop.

20a is 99% a dead socket
Intel don't build a specific foundry for one cpu model and then delete it and build a new on when they are done.


Who actually makes them anyway I thought TSMC did? and intel just packages the chip( which doesn't mean plastic and cardboard.

google is full of articles like saying they cancelled 20a and used someone else probably tsmc to build the chiplets
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20A and 18A are almost the same thing. “20A foundries” can manufacture 18A , the same way that Intel 4 foundries will transition to Intel 3 with almost no investment.

Actually, in the latest 18A revision ppw over Intel 3 was the same for both nodes. 20A only know product were some Core 3 200. It was pretty much a test node to derisk 18A, but 18A is -according to Intel- ahead of schedule. There is no product that will move from 20A to TSMC.
 
Tetras said:
They fixed it! Just delete the P-Cores and gaming is good again.
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Yeah I was wondering if changing core configs might result in significant performance differences.

What does 'physically separated core config' mean?

EDIT - Bah! don't have a working twitter account (google login fails). I wonder if it's even worth it.
 
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Ga1y6aoXYAAC1BX


Oh, I see, In this case they are disabling the E-cores at the top, and 2 P -cores at the bottom (and it actually functions better). What a stupid design.

So, maybe if they built a P core only model (e.g. with 8 cores), it would help a lot with latency issues.
 
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The difference in 0.2% lows even running at default clock speeds is insane, just by disabling some of the cores.

Doesn't this mean that a 6-P core CPU like the 245K might be better value? I will look at the core layout...

EDIT - Can't find the tile floor plan for the 245K. Intel hasn't published it afaik.
 
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They need to build an 8P-core CPU with a contiguous design...

I don't understand Intel's stubborn addiction to E-Core (+ P core) only designs on desktop. They can have a few 'added on to the end' it looks like, but anything else makes no sense. They need to be easy to disable also.
 
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Minstadave said:
What an absolute garbage CPU :cry:

Intel mocked AMD for "glueing together dies" now not only are they doing the same, they're doing it badly!
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Supervisor: "DUDE, what are you doing?"
Employee: "I'm gluing the dies"
Supervisor: "That one is upside down"
Employee: "****"
Supervisor: "Never mind. How many have you done already?"
Employee: "Twelve million"
Supervisor: "****"
 
I just remembered - Isn't the current line-up of K Arrow Lake CPUs all built from the same chip / SKU?

The cheaper models just have part of the chip disabled.

So the layout will be the same, so there's no escaping the issue on the 245K...

It seems like E-cores should have been just for mobile CPUs, for the 12th, 13th, 14th and 15th gen.

They could have used an E-core only design. That would've made even more sense with the 15th gen, which has significant improvements to the E-cores.

P-cores could have have just meant desktop :rolleyes:
 
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g67575 said:
Oh, I see, In this case they are disabling the E-cores at the top, and 2 P -cores at the bottom (and it actually functions better). What a stupid design.

So, maybe if they built a P core only model (e.g. with 8 cores), it would help a lot with latency issues.
Click to expand...
Idk if that's the problem, I mean... I assume Intel would have been aware it would have a latency penalty to spread the E-Cores out like that. I wonder if something else is going on.
 
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