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Rocket lake leaks

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Another forum. Gear 2 mode.
 
humbug said:
What have they done to it to bring the interconnect latency up to Zen 3 levels?
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Grim5 said:
its brand new architecture and this could just be the normal latency for this design
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Don't forget that Rocket Lake was originally designed for their 10nm process, but had to be backported to 14nm. This explains the core count and clock sped regression, but it's entirely possible that the move to 14nm has just made the interconnect traces too long to operate at the speeds they were designed for. It's not the design that's the issue, it's the hatchet job moving to a chunkier node than it was intended for.

But we'll never know for sure because Rocket Lake/Cypress Cove is not getting iterated, its just getting binned off in favour of Golden Cove for Alder Lake and Sapphire Rapids.
 
Grim5 said:
It's not in the 40s at all, latency on the 11700k is mid to high 50s
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I would guess so as well though @Robert896r1 is rather adept at memory tuning and even on Z390 with good memory and strong IMC it is possible to tune 3733Mhz to get below ~45ns. My query was more to do with if it was still possible on Rocket Lake or is it like Ryzen 5000 where it is really difficult to get below 50ns.

Though the way that it is looking now a certain member is going to have to spin like Kayleigh McEnany to make this into a 'win' for Intel.
 
MartinPrince said:
Thanks for the insight.

It's a little troubling that you are finding this 3733Mhz sync limit which seems quite a retrograde move, though I'm curious as to the reason why it is necessary. Are the memory latencies you are seeing already in the low 40ns when you're at 3733Mhz?

The ability to tune memory without sync limits is the main reason that my tuned 9700K can still hang with my tuned 5800X in some lower threaded applications, though as we are a niche clientele then getting the most performance out of the CPU at stock is probably the priority - similar to what AMD have been doing.
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once bios is mature and you can boost ring higher you can daily sub 40 but overall BW will be low. Hopefully at launch when we get architecture breakdowns where we will learn why they went sync but hard to guess now.

11900k sub 40ns. Ring is limited in current asus bios. Even if you loosen up the timings below, you should be able to reclaim that latency loss by boosting ring and stay sub 40ns

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Compared to my buddy’s tuned 10900k:
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And my 9900k:
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We will test SR next on RKL to see what the max frequency sync limit is and whether it’s higher for SR than 3733.
 
Going to be interesting to see what you can expect with just out of the box performance vs 10th Gen, and not spending umpteen hours messing around with it, just what the 99% will see when they buy one.
Is it going to be slower than both 10th Gen and 5xxx Ryzen? That would be the important question, I mean if you need to buy special RAM and tweak it for hours who'd do that. :p ;)
 
Robert896r1 said:
once bios is mature and you can boost ring higher you can daily sub 40 but overall BW will be low. Hopefully at launch when we get architecture breakdowns where we will learn why they went sync but hard to guess now.

11900k sub 40ns. Ring is limited in current asus bios. Even if you loosen up the timings below, you should be able to reclaim that latency loss by boosting ring and stay sub 40ns

201600mtn6fle5qklkp8lp.png


Compared to my buddy’s tuned 10900k:
4500161717op.png


And my 9900k:
unknown.png


We will test SR next on RKL to see what the max frequency sync limit is and whether it’s higher for SR than 3733.
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Very interesting. Getting 3733Mhz to C13 is going to be a niche position and that sync limit is going to be mightily disappointing for overclockers.

Very impressive bandwidth on the Z490 and your 32.5ns latency is probably the reason that I see your single threaded game performance is as good as it is. ;) The best I could get my 5800X to is a synced 3800Mhz C14-14-14-31 1T which gives me 57ns. (though also look at that below par Write)
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PS. tRAS normally is tCL + tRCD + 2 and generally there is a penalty performance for going lower. Is your performance the same/worse/better if you set your tRAS to 34?
 
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@MartinPrince what we learned from extensive testing and data correlation is a lot of these rules are made up and just passed on until they eventually become common place. There's no hard limit for the tras rule or twr = trp x 2 etc. And other things that were encouraged before like lowering tcwl as low as it goes creates a gap that limits the floor on tertiaries ultimately leading to worse performance.
 
Robert896r1 said:
@MartinPrince what we learned from extensive testing and data correlation is a lot of these rules are made up and just passed on until they eventually become common place. There's no hard limit for the tras rule or twr = trp x 2 etc. And other things that were encouraged before like lowering tcwl as low as it goes creates a gap that limits the floor on tertiaries ultimately leading to worse performance.
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Ah, good to know. I can get my tRAS down to 28 but always left it at 32 as I didn't really find a definite improvement. I generally set tCWL to tCL - 1 but might try your tCWL = tCL. Your tWTR_S/L are impressively at the lowest but your motherboard/memory/IMC can do that. Plus you have the ability to change RTL's and IO-L's whereas I'm at the mercy of how my motherboard trains.

Anyway, it looks like the advantage Intel had with the ability to use and benefit from higher frequency memory has all but evaporated. Let's see how much IPC improvement those under pressure Intel engineers have managed to eek out with Rocket Lake.
 
Yeah looks trash wonder why they even bothered going to the trouble and expense of backporting unless they wanted to hedge bets in case Alderlake was delayed as that should be hopefully much better.

Some good prices now for the 10th gen parts recently though.
 
Toasty said:
Yeah looks trash wonder why they even bothered going to the trouble and expense of backporting unless they wanted to hedge bets in case Alderlake was delayed as that should be hopefully much better.

Some good prices now for the 10th gen parts recently though.
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Really hard to know how Alder Lake well land though, as BIG.little (not big.LITTLE was that's the ARm term - and possibly trademark) is totally new to x86.
Still, 10nm should give them more transistors to play with. Against that, max clocks will probably go down.
 
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