You can expect to get it as low as 65ns after much tweaking. The gain won't be noticeable. I would do it just for knowing the CPU runs as fast as it can.
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AMD Zen 2 (Ryzen 3000) - *** NO COMPETITOR HINTING ***
- Thread starter Jamin280672
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Soldato
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Is that your manual oc 4.4?
I can run that too but I rather run 3733Mhz and reduce the voltage on the RAM since for gaming the difference will be 0. I was getting 63.5ns latency on 3800Mhz and 64.3ns on 3733Mhz.
What RAM kits are you using?
I've managed 3800/1900 but at 16-16-16-16-36 1T (1.38v) with 3866 8-Pack kit with decent sub timings which scores me around 63.5ns
Went from a 2700x to a 3900x a massive difference.
Soldato
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I can well believe it, it's the thought of a 3900X in a Crosshair 6 Hero that I am not too sure about. I don't know how well it'll work.
Cheers, your read score is higher than mine at C16 but my latency score is lower at 63.5ns, better sub timings maybe??
Ouch, expensive.
Soldato
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What's the logic behind tightening timings? Is there some mathematical formula that says when x = y values a, b, & c can be between a certain number?
What stops someone just putting in nonsense for those timings?
16 107 332 1 5 at 3600MHz
What stops someone just putting in nonsense for those timings?
16 107 332 1 5 at 3600MHz
When you go to adjust the timings there is a description for what each one does (at least my BIOS has it), the less time it takes to do each command, the quicker your ram responds. It also shows the margins of what is the minimum and maximum on each one.What's the logic behind tightening timings? Is there some mathematical formula that says when x = y values a, b, & c can be between a certain number?
What stops someone just putting in nonsense for those timings?
16 107 332 1 5 at 3600MHz
Soldato
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I see. My board doesn't have that feature unfortunately.
Soldato
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What's the logic behind tightening timings? Is there some mathematical formula that says when x = y values a, b, & c can be between a certain number?
What stops someone just putting in nonsense for those timings?
16 107 332 1 5 at 3600MHz
I think there are a couple of things that are related.
Usually the formula tRC = tRAS + tRP should be followed though the calc doesnt alsways follow that rule. Even values for tWRWR SCL and RDRD SCL too are usually more stable. I guess there are related algorythms in the DRAM calc that the author understands. Still not got my 3600Mhz ram stable at 3600Mhz yet. I found the diagrams on the techpowerup website useful for the process for tuning the RAM, put together by the DRAM calc guy. DO NOT DISTURB THE SEQUENCE!
https://www.techpowerup.com/review/amd-ryzen-memory-tweaking-overclocking-guide/5.html
Really? Even when you get into the sub timings section of the BIOS? Its crazy they let you modify it without explaining what they do. Obviously not everyone knows what each one does, including me, but they should at least give you an idea.
Indeed!
Shamelessly stolen from RAMAD:
Primary timings:
- tCL, tRCD (RD, WR), tRP, tRAS and CMD (command rate), which you can set as your RAM can tolerate, i.e: 16-18-18-18-36-1T or 2T they can also be calculated, but there is always some headroom with these timings.
Secondary timings:
- tRC = tRP + tRAS (I add 2 clocks more for stability, but this is the user call)
- tRRD_S, tRRD_L and tFAW. These depends on the Memory Data Interleaving size, ½KB, 1KB or 2KB so make sure that you use the value for the same page size when calculating them. The lowest value for tFAW is 16 clocks, never use values lower than 16CK even if you are getting a lower value when calculating.
- tWR and tRTP. tRTP is always half of tWR.
- tRFC, tRFC2, tRFC4. Those are refreshing timings which are temperature dependent. tRFC is in effect below 85C, tRFC2 between 85C and 95C, tRFC4 is when the RAM reaches 95C. Changing from 1, to 2 to 4 is automated by the RAM which is triggered when the RAM temperature is in or reaches one of the intervals above. I use default values for the frequency that I'm running my RAM at.
- tCKE (Clock Enabled). Timing which all above timings depends on because it syncs operations starts. The whole RAM cycle starts when triggered. If CKE = 8CK then the RAM waits 8 clocks before getting a new window to start next operation. It sounds like many clocks but the chances of waiting 8 clocks is very slim when our timings are 14+ clocks. 1 or 2 CK used to work well with earlier AGESA (before 1.0.0.4) but I have seen it reduce stability when set low on latest AGESA , so I'm using the default value with newer AGESA versions.
-tCWL. This is equal to tCL or tCL-1CK or -2CK. Use the value your RAM likes.
The rest of the timings that we have on this platform are called "Turn Around". They don't exist on any RAM die data sheet because they are IMC timings (the way I understand them, because I could never find them on any document), such as tRDWR which means: read to write delay, tRDRDScl: read to read same channel, tRDRDSd: read to read same DIMM (same memory stick) and so on.
They are almost identical on all Ryzen CPUs (+- 1 to 2 clocks). The only rule that I made for my self is setting is: tRDWR (read to write delay) = 2 x tRWRD (write to read delay).
So all you need is to find the data sheet for your RAM die and start calculating your own timings, just remember to round up the calculated timings when using them.