Sounds like a potential issue with microcode and new Agesa incoming. Just very weird if they missed it before, but then again they increased cache potentially because of this exact reason? But that would mean it wouldn't be visible in standard use aside specific latency tests. Many questions to be answered!
Edit: I just found a post showing AMD slides seemingly confirming they changed inter-core topology in Zen5 from ringbus to mesh. The latter has been used in servers for large number of cores CPUs and it indeed could explain higher inter-core latency than previous topology from Zen4. In other words, it would seem Zen5 based Ryzen CPUs are structured more like server CPUs for productivity and not for gaming. I wonder if this is what AMD meant saying x3D chips will have more changes than just cache added this time - different inter-core topology? But that would mean they would be segmenting Ryzen CPUs between productivity (and general use) Vs purely gaming ones even more than before. And possibly slap even higher prices on x3D ones.