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AMD Zen 5 rumours

These will be reviewed again when the 800 series motherboards come out, AMD have until then to continue R&D on the microcode, that's copium i know.... but i think these things are actually pretty good CPU's, more time in the oven might just get them across the line.

I have no doubt AMD are busy busy working on them....
 
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I was looking at the 7800X3D to replace my 5 7600 but after watching this ime not sure
eny thoughts im on a 4k monitor
 
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I was looking at the 7800X3D to replace my 5 7600 but after watching this ime not sure
eny thoughts im on a 4k monitor

High resolution like 4K is primarily a GPU load, your GPU isn't generation enough frame rates for the CPU to struggle to keep up with, that's what a CPU bottleneck is, a given situation where your GPU can pump out 300 FPS but your CPU can only manage 200 FPS, so the GPU will not be working at full capacity, limited by the CPU to 200 FPS.
If you take the same situation and crank the resolution up to a point where your GPU can only manage 150 FPS then your 200 FPS CPU has no problems.
 
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If you're running something Like MSI After Burner OSD keep your eye on GPU utilisation, if that drops below 95% for an extended time then your CPU isn't fast enough to keep up with the GPU, if its always 95% or higher then adding a faster CPU won't make any difference.
 
Consider - we still don't know exactly why AMD recalled/delayed initial launch, as far as I'm aware there's zero evidence to suggest a significant change in the bus technology, the TDP/power delivery has been cut. Quite late on I may add, and I'm not convinced this is purely for "efficiency" claims, the 9950X should have the top binned cores for at least one of it's CCXs. If this theory of aggressive core parking due to deliberate software changes pans out to be true then the next question is what do all of these things suggest?

Is it unreasonable to suggest that AMD are simply hitting the limits of safety on this node process, and wish to avoid a similar physically destructive issue that Intel are dealing with?
 
Is it unreasonable to suggest that AMD are simply hitting the limits of safety on this node process, and wish to avoid a similar physically destructive issue that Intel are dealing with?

There are various hints that the production quality of the silicon in volume production hasn't matched up to expectations at too late a stage to fix it for release - but that doesn't account for stuff like the latency issues. And ultimately there seems to be a bottleneck somewhere architecture wise likely bus or cache related.
 
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Consider - we still don't know exactly why AMD recalled/delayed initial launch, as far as I'm aware there's zero evidence to suggest a significant change in the bus technology, the TDP/power delivery has been cut. Quite late on I may add, and I'm not convinced this is purely for "efficiency" claims, the 9950X should have the top binned cores for at least one of it's CCXs. If this theory of aggressive core parking due to deliberate software changes pans out to be true then the next question is what do all of these things suggest?

Is it unreasonable to suggest that AMD are simply hitting the limits of safety on this node process, and wish to avoid a similar physically destructive issue that Intel are dealing with?
Yeah, Anad might be on to something.

Compared to the Ryzen 9 7950X, we are seeing a slight increase in latencies within a single CCX. The SMT "advantage", where two logical cores sharing a single physical core have a lower latency, appears to be gone. Instead, latencies are consistently around 20ns from any logical core to any other logical core within a single CCX. That average is slightly up from 18ns on the 7950X, though it's not clear what the chief contributing factor is.

More significantly – and worryingly so – are the inter-CCD latencies. That is, the latency to go from a core on one CCD to a core on the other CCD. AMD's multi-CCD Ryzen designs have always taken a penalty here, as communicating between different CCDs means taking a long trek through AMD's Infinity Fabric to the IOD and back out to the other CCD. But the inter-CCD latencies are much higher here than we were expecting.

For reference, on the Ryzen 9 7950X, going to another CCD is around 76ns. But in Ryzen 9 9950X, we're seeing an average latency of 180ns, over twice the cost of the previous generation of Ryzen. Making this all the more confusing, Granite Ridge (desktop Ryzen 9000) reuses the same IOD and Infinity Fabric configuration as Raphael (Ryzen 7000) – all AMD has done is swap out the Zen 4 CCDs for Zen 5 CCDs. So by all expectations, we should not be seeing significantly higher inter-CCD latency here.

Our current working theory is that this is a side-effect of AMD's core parking changes for Ryzen 9000. That cores are being aggressively put to sleep, and that as a result, it's taking an extra 100ns to wake them up. If that is correct, then our core-to-core latency test is just about the worst case scenario for that strategy, as it's sending data between cores in short bursts, rather than running a sustained workload that keeps the cores alive over the long-haul.

20ns from 18ns is nothing, and its still a 50% improvement from Zen 3, see slide below.

The 100ns increase from inter CCD communication. so that does matter, it explains why its necessary to run the Game Bar CCD parking thing for games as if it was a multi CCD X3D chip, i'm not sure about the theory of AMD aggressively putting cores to sleep and the added 100ns is them waking up, because if that was true that would also show in the core to core latency, and 18 vs 20ns i would argue it doesn't.
So i wonder if its the Infinity Fabric on the IO die that has some sort of falling in and out of sleep power saving feature? One of the complaints about Ryzen Desktop CPU's is the relatively high idle power consumption, that being 10 to 15 watts, this is due to the IO die always being active to keep the Infinity Fabric alive.

If its something like that, they can fix this with Microcode.

xLByhRG.jpeg


fAT33eY.png
 
20ns from 18ns is nothing
more suspicious is increase in latency between two SMT threads on same core from 5-6 to 18-19

this smells like a result of vulnerability mitigation, spending time to synchronise with higher lever memory
and maybe the real reason why Intel gave up on hyperthreading, unable to solve this problem without taking same kind of penalty
 
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more suspicious is increase in latency between two SMT threads on same core from 5-6 to 18-19

this smells like a result of vulnerability mitigation, spending time to synchronise with higher lever memory
and maybe the real reason why Intel gave up on hyperthreading, unable to solve this problem without taking same kind of penalty

True, i missed that bit.

I do find some of these security mitigations a bit OTT, if someone can hack in to my computer from the Internet then yeah, fix that _____ but if it takes someone with equipment needed to hack in to my motherboard physically at my computer..... i'm not worried about that.
 
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True, i missed that bit.

I do find some of these security mitigations a bit OTT, if someone can hack in to my computer from the Internet then yeah, fix that _____ but if it takes someone with equipment needed to hack in to my motherboard physically at my computer..... i'm not worried about that.
yeah, thats definitely driven by server world
where a compute provider will commonly be running software from different customers on same CPU, definitely want to eliminate a possibility of one client snooping/hacking another
 
Anand mentioned the latency may be due to the overly aggressive core-parking. It would be worth redoing their test after increasing minimum C-states, to prevent the core's going into such a deep sleep. Therefore they "wake" much quicker.
We used to do this all the time to improve responsiveness of worker threads.

I'm convinced all their problems are due to overly-aggressive core sleeping, and the much lower base-clock speed causing it to take longer to get to full speed.
 
and maybe the real reason why Intel gave up on hyperthreading, unable to solve this problem without taking same kind of penalty

I definitely don't buy Intel's performance/power arguments for abandoning hyper-threading and IMO we'll see it back sooner rather than later.
 
Just got my sample from a UK retailer, not OcuK.

SP118.

BIOS Screenshot


360 AIO + Liquid Metal. Ran it stock vs stock vs my 7950X3D. One run of Cinebench each, no warm up runs. BIOS stock default settings, so FCLK at default (1733Mhz for 7950X3D) and 1800Mhz for 9950X).

7950X3D


9950X


EDIT

9950X with PBO Enabled, max board power limits, + medium load boost it, + Auto OC +200Mhz, but stock memory freq/timings/fclk clocks. No curve optimiser/shaper.


EDIT 2

9950X with PBO Enabled and -10 all core negative curve optimiser applied, + max board power limits, + medium load boost it, + Auto OC +200Mhz, but stock memory freq/timings/fclk clocks.


EDIT 3
9950X with PBO Enabled and -14 all core negative curve optimiser applied, + max board power limits, + medium load boost it, + Auto OC +200Mhz, but stock memory freq/timings/fclk clocks. Anything more than -14 all core negative curve optimiser is unstable.


I need to get a memory frequency overclock and FCLK overclock on there too as currently running at 4800Mhz and 1800Mhz respectively with CL40. :p


9950X is about 14% faster stock for stock and runs cooler at higher power. 7950X3D is drawing a lot less power though. :)

Note: This is not a clean OS install. Just took my 7950X3D out and installed the 9950X.
 
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Hmmm I'm still honestly not understanding the chips. This still clearly shows cinebench R23 is better but generally nothing at all in anything else that is worth the extra power/heat compared.

I don't understand how people are expecting anything from the x3D honestly to what we currently have.
 
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