-
Competitor rules
Please remember that any mention of competitors, hinting at competitors or offering to provide details of competitors will result in an account suspension. The full rules can be found under the 'Terms and Rules' link in the bottom right corner of your screen. Just don't mention competitors in any way, shape or form and you'll be OK.
AMD Zen 2 (Ryzen 3000) - *** NO COMPETITOR HINTING ***
- Thread starter Jamin280672
- Start date
Yeah, it's nothing I have seen officially (nor do I really expect them to explain their marketing BS), but there's no other explanation for it.
Even assuming the 3950X chiplets are better binned, you still have more of each one enabled, which should logically increase the TDP. There's more to it than just better binning on this one.
Associate
- Joined
- 2 Jan 2019
- Posts
- 617
Yup.
By my calculations 3rd gen Ryzen would need to be going to memory 36-40% less often as a result of the doubled L3 in order to bring effective latency down to being on a par with 9th gen Intel. IIRC, the initial indications are 10ns to L3 and 67ns to memory, versus 10ns to L3 and 47ns to memory with Intel.
I thought asmedia developed or are developing a PCI-e 4.0 chipset for B550
The last I heard, PCIe 4.0 was being kept for X570 boards because of the expenses involved in the board design. Whether that has changed, I don't know.
Just a scant browse confirms what you said at least untill 2020. So realistically what your getting is X470 rebrand to b550 by looks of it
Where do you get your "initial indications" from ? Even Zen+ get's better latency than 10ns to L3 and 67ns to Memory and that's with Memory at 3533Mhz. Zen 2's sweet spot is supposed to be 3733Mhz.
I would expect Zen 2 Memory to be 58/59ns and L3 8/9ns
With the possible benefit of better VRM designs and cheaper introductory pricing, I would be fine with that, given how the X570 products are looking.
I'm interested to see what if anything the extra L3 on the 3900X does Vs the 3800X.
Associate
- Joined
- 2 Jan 2019
- Posts
- 617
They were taken from various other benchmarks where a common theme of 67ns was showing up, which for the most part has been consistent with what Zen+ was offering.Where do you get your "initial indications" from ? Even Zen+ get's better latency than 10ns to L3 and 67ns to Memory and that's with Memory at 3533Mhz. Zen 2's sweet spot is supposed to be 3733Mhz.
I would expect Zen 2 Memory to be 58/59ns and L3 8/9ns
Regarding the L3 figure, I vaguely remember seeing an earlier AIDA benchmark for Zen 2 being at 10ns, though it matters little because I've assumed exactly the same figure for Intel.
Perhaps I should have been more clear with that, all L1/2/3 being equal latency, Zen 2 having double L3 cache would need to go to memory 36-40% less often with 67ns memory latency (or 25% less often with 59ns) for effective memory latency to be the same as 9th gen Intel.
Last edited:
Math is not my strong point but we know the increase in L3 has increased it's latency from 35 cycles to 40, latency is a tricky thing to measure though as it depends on where the two points you're measuring from are and if you're just measuring first word access times, trying to work it out on paper gives me headaches.
Associate
- Joined
- 2 Jan 2019
- Posts
- 617
The real take home is the headline memory latency number means very little; Zen 2 will require fewer trips to memory due to it's design. Fewer trips to memory equates to lower real world latency. Lower real world latency equates to better real world performance.
What matters is how much the increase in L3 cache reduces the trips required to memory. It'll vary by workload, clearly.
My instinct tells me that node shrinks with next generations might be taken up by larger L3 rather than extra cores; they already take up around 50% of die space.
What matters is how much the increase in L3 cache reduces the trips required to memory. It'll vary by workload, clearly.
My instinct tells me that node shrinks with next generations might be taken up by larger L3 rather than extra cores; they already take up around 50% of die space.
Oh i fully agree. The fewer trips to memory, the better all round for a wide variety of workloads particularly gaming. That's why Lisa Su emphasized gaming in her presentation.
While using old separate high and low side FETs+drivers design they're certainly decent.
B450 Carbon beats half the Asus/Gigabyte boards with proper four phases.
Plus includes BIOS flashback without CPU/memory/GPU.
And X470 Carbon rises number of phases from four to five, though there's that IO cover marketing BS excrement to decrease VRM cooling.
So VRM temps might actually not be that much better, but extra phase should improve output ripple/voltage regulation.
Though compared to X570 that's likely going to be very low end level and good amount better and beefier VRMs exist in current board.
Thermodynamics, which if we had wrong would make most machinery not work, tells this:
Energy can't disappear, or appear from nowhere. It can only change form.
That means heat output equals to electric power consumption.
Intel's gross lying/misleading in TDP to hide full load power consumption at hyped speed is entirely different thing.
Though of course if Zen2s run at lower voltage, that increases current draw making them harder load per watt.
Anyway better VRMs like six phase IR3555 should have plenty enough reserve for higher current.
Yes, but what does that have to do with the Crosshair VIII Hero? Just because Asus are slapping on a few more components and charging a fortune doesn't mean the tier below will be just as expensive, and it doesn't mean it'll be much more affordable. We don't know yet.
Intel confuses people because they put the "@ 3.6 GHz" in the ID string of the CPU itself. It does not mean the CPU is running at that base frequency, because in almost all cases it will actually be running at its boost clocks (e.g. 5.0 GHz for i9-9900K on a single core at stock).
No, the software isn't "reading" any frequency from any "firmware" at all.
Ok, so maybe you answer his question then, if not that then what?